eZ80F92 Development Kit
User Manual
UM013904-0203
PRELIMINARY
Appendix A
73
Appendix A
General Array Logic Equations
This appendix shows the equations for disabling the Ethernet signals pro-
vided by the U10 and U15 General Array Logic (GAL) devices.
U10 Address Decoder
//`define
idle
2'b00
//`define
state1
2'b01
//`define
state2
2'b11
//`define
state3
2'b10
// FOR eZ80 Development Platform Rev B
// This PAL generates 4 memory chip selects
module f92_decod(
nCS_EX, //Enables Extension Module's Memory when Low
nFL_DIS,//when Low WEB Module Flash is disabled (nDIS_FL=0),
//when High nDIS_FL depends upon state of nmemenX
nCS0,
A7,
//A23
A6,
//A22
A5,
//A21
A4,
//A20
A3,
//A19
A2,
//A18
A1,
//A17
A0,
//A16
nCS2,
