User Manual
UM015201-0603
I/O Connector
ZiLOG Development Platforms
eZ80
®
Sales Demonstration Platform
13
WAIT
PU 2k
OUT
Driving the WAIT pin Low forces the
eZ80
®
CPU to
provide additional clock cycles for an external periph-
eral or external memory to complete its READ or
WRITE operation.
HALT_SLP
IN, Active Low A Low on this pin indicates that the eZ80
®
CPU
enters either HALT or SLEEP mode because of exe-
cution of either a HALT or SLP instruction.
NMI
PU 10K
Schmitt Trigger
OUT, Active
Low
The NMI input is a higher priority input than the
maskable interrupts. It is always recognized at the
end of an instruction, regardless of the state of the
interrupt enable control bits. This input includes a
Schmitt trigger to allow RC rise times. This external
NMI signal is combined with an internal NMI signal
generated from the WDT block before being con-
nected to the NMI input of the eZ80
®
CPU.
V
CC
n/a
3.3V Supply Input Pin.
GND
n/a
V
SS
/Ground (0V)
Table 3. I/O Connector Pin Identification (Continued)
Function
Pull
Up/Down
Signal
Direction
Description
