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CIRCUIT DESCRIPTION
ON THE TERMINAL PWB:
A/V Selector I401
Sub Video Chroma I403
ON THE DEFLECTION PWB:
Sweep Control I701
ON THE SUB VIDEO PWB (2H VIDEO):
Rainforest IX01
ON THE SURROUND PWB:
Front Audio Control IS03
Center/LFT/PinP Audio Control IS08
Surround Board DAC3 IS01
Front Equalizer IS05
Center Equalizer IS10
Rear Audio Control IS11
Audio DSP (Digital Signal Processor) DSP Unit HC4051
The following explanation will deal with the communication paths used between the Microprocessor and the
respected ICs.
ON THE SIGNAL PWB:
Main Tuner U201
The Microprocessor controls the Main Tuner by Clock, Data and Enable lines. Clock, Data and Enable
lines for the Main Tuner are output from the Microprocessor at pins (20 Clock, 21 Data and 44
FEENABLE1) respectively. Pin (44) FEENABLE1 goes directly to the Main Tuner at pin (6), where as the
Clock and Data lines must be routed through the Level Shift IC I014 to be brought up to 5V. Clock and
Data from the Microprocessor arrive at I014 (Level Shift) at pins 2 and pin 3 and are output at pin18 and
pin17. They arrive at the Main Tuner at pins (4 and 5).
PinP Tuner U202
The only difference for the PinP tuner control lines is related to the PinP Enable line. This is output from the
Microprocessor pin 43 (FEENABLE2) to the PinP Tuner at pin 17. Clock and Data are the same as for the
Main Tuner.
EEPROM I002
The EEPROM is ROM for many different functions of the Microprocessor. Channel Scan or Memory List,
Customer set-ups for Video, Audio, Surround etc are memorized as well. In addition, some of the
Microprocessors internal sub routines have variables that are stored in the EEPROM, such as the window
for Closed Caption detection. Data and Clock lines are SDA1 from pin (2) of the Microprocessor to pin
(5) of the EEPROM and SCL2 from pin (3) of the Microprocessor to pin (6) of the EEPROM. Data
travels in both directions on the Data line.
