3-48
3-49
HD-1
SYS_CLK
VDP_CLK
NTSC_CLK
MAIN_PWM
FR_RATE60
27MHz
System
CPLD
VCXO
27MHz
49FCT
3805
ICS621M
Clock
Buffer
Clock
Synthesis
Control
Output
Buffer
Clock
Buffer
Clock
Synthesis
Control
Output
Buffer
Output
Buffer
ICS501
Clock
OSC
PLL Clock
Multiplayer
& ROM
Output
Buffer
27MHz
AC-3 Decoder
Clock
74.175MHz or 81MHz
27MHz
74.175MHz or 81MHz
74LCX
253
S1
S0
81MHz
PSEUDO_60
SEL HD CLK
CP_INT/PRG
SEL_HD_CLK
CP_INT/PRG
PSEUDO_60
81MHz
PLD_81M
NT2CLK
5) VIDEO PLL BLOCK DIAGRAM
Summary of Contents for HDR230
Page 28: ......
Page 34: ......
Page 37: ......
Page 38: ...3 17 3 18 4 WAVEFORMS 1 DIGITAL SYSTEM CLOCK GENERATOR PART 1 2 3...
Page 39: ...3 19 3 20 2 DIGITAL SYSTEM SYSTEM MEMORY PART 1 2 3...
Page 40: ...3 21 3 22 3 VIDEO PLL PART 1 2...
Page 41: ...3 23 3 24 4 VIDEO OUTPUT CONNECTOR PART 1 2 3 BMK800 BMK800 BMK800 33PF 33PF 33PF...
Page 43: ...3 27 3 28 6 PVR CLOCK PART 1 2 3...
Page 44: ...3 29 3 30 7 VSB VSB DECODER PART 1...
Page 45: ...3 31 3 32 8 VSB DOWN CONVERTER PART 1...
Page 46: ...3 33 3 34 9 MICOM DOWN CONVERTER PART 1...
Page 47: ......
Page 65: ...3 74 3 75 10 VSB CIRCUIT DIAGRAM IF VSB TP Data clock error valid 03 3 15 HDR230 DNS...
Page 67: ...3 78 3 79 12 POWER IF COM VIDEO CIRCUIT DIAGRAM CVBS OUT Y OUT C OUT 03 3 15 HDR230...
Page 68: ...3 80 3 81 13 FRONT CIRCUIT DIAGRAM RIGHT LEFT 03 3 15 HDR230...
Page 69: ...3 82 3 83 8 PRINTED CIRCUIT DIAGRAMS 1 DIGITAL MAIN PRINTED CIRCUIT DIAGRAMS TOP...
Page 70: ...3 84 3 85 2 DIGITAL MAIN PRINTED CIRCUIT DIAGRAMS BOTTOM...
Page 72: ...3 88 3 89 5 POWER PRINTED CIRCUIT DIAGRAM LOCATION GUIDDE...
