Zenith HDR230, Service Manual

Page: 50 / 94

3-44 3-45
3) SYSTEM BLOCK DIAGRAM
16Mbyte
32Mbyte System Memor y
8M x 16
(4 bank )
Address
(0:11)
Data
(0:16)
BA0
BA1
DQM
(0:1)
VCC
GND
Data
(16-31)
BA0
BA1
CS
/WE
/CAS
/RAS
CLK
BSE0
/WE
/CAS
/RAS
CLK
DQM(2,3)
16Mbyte
8M x 16
(4 bank )
Address
(0:11)
Data
(0:16)
BA0
BA1
DQM
(0:1)
VCC
GND
Data
(0-15)
M_Address (0-11)
BA0
BA1
CS
/WE
/CAS
/RAS
CLK
BSE0
/WE
/CAS
/RAS
CLK
DQM(0,1)
Address
(0-11)
100MHz Processor Bus(PLB) 64-bit
OCM
Ctrl
4K
SRAM
Interrupt
Control
Ethernet
MAL
DMA
Ctrl
PCI
Bridge
SDRAM
Controller
SRAM/ROM
Peripheral
Controller
External
Bus Master
Controller
OPB
Bridge
O
n
-chip Peripheral BUS(OPB)
UART
I2C
GPIO
Timers I-OCM
D-OCM
JTAG Trace
50MHz
Arb
Clock
Control
Power
Magmnt
Code Decompression
UART
16K, I-C 8K,D-C
MMU
DCU ICU
PPC 405GP
CPU Core
MII
PPC405GP
[456-PBGA,
2.5V, 3.3V]
8Mbyte Flash Memory
D0~D15
D16~D31
2M x 16
29DL323TE
D0~D15
A1~A21
/CE
/RESET
/OE
/WE
WP/ACC
/BYTE
A0
VCC
A2~A22
/WE
/RESET
/OE
2M x 16
29DL323TE
D0~D15
A1~A21
/CE
/RESET
/OE
/WE
WP/ACC
/BYTE
A0
VCC
/1ST_CE0
A2~A22
/WE
/RESET
/OE
System CPLD
EPM3128A
A0~A4
A20~A23
D0~D7
Control
Signals
In
Control
Signals
Out
RS-232C
Driver
MAX232A
I2C Bus
Driver
PCF8584
Clock
Generator
ICS387
14.318MHz
33.3MHz- 1
12MHz
33.3MHz- 2
M_Data (0-31)
/1ST_CE0
S_Address (0-22)
S_Data (0-31) S_Data (0-7)
I2C_A
I2C_C
SVC
PORT
UART
SIGNAL
UART
Ω≈
ȣ
33.3MHz- 1
PCI_Bus
Video
Video Output