Zenith D52WLCD Series, Service Manual

Page: 28 / 71

D52WLCD
28
CIRCUITS
CIRCUIT DESCRIPTIONS
(3) Block Diagram
(4) Architecture
DTV ready video chip
NTSC/PC/STB
PIP/POP/split - screen/zoom
60/50Hz display
2- D graphic with OSD
Color space conversion
NTSC up - conversion
3xDAC, PLL
SDRAM
8(4) Mbytes
NTSC
decoder
S/W
1080 I/
768(720)P/
480P(I)/
576P(I),
16:9 or 4:3,
analog or digital
Composite 1
VGA
(RGB)
A
/
D
STB
( YPbPr)
S- Video 1
RGB or
YIQ or
YUV or
YCbCr
(24)
Composite 2
S- Video 2
YIQ or
YUV or
YCbCr
(16)
CPU
STB2
( YPbPr)
A
/
D
Display PLL
NTSC
decoder
Grap .
Proc.
Grap .
Proc.
CSC
/LUT
CSC
/LUT
Host I/F
Host I/F
CSC
CSC
MU
X
Sync
Generator
Sync
Generator
4 MB or 8MB
SDRAM
RGB or
YIQ or
YUV or
YCbCr
(24)
Input B
Input A
YPbPr /RGB
(1080I, 768P,
720P, 480P)
Y
Enhance
Y
Enhance
Format
Converter
Format
Converter
Format
Converter
Format
Converter
YIQ or
YUV or
YCbCr
(16)
DAC
DAC
(1080 I, 720P,
480P, 480I,
VGA)
8 M mode
8MB Memory : 8.389MB
Graphic Memory : 1.503MB
(>540x1920x1=1.037MB)
SDRAM
Interface
SDRAM
Interface
4 M mode
4MB Memory : 4.419MB
Graphic Memory : 0.526MB
(>540x960x1=0.518MB)
External
Intf .
External
Intf .
Sw
it
c
h
CSC
CSC
External
Intf .
External
Intf .