Z-World RabbitCore RCM3200, User Manual

Page: 85 / 92

User’s Manual 81
The Quadrature Decoder generates an interrupt when the counter increments from 0x00 to
0x01 or when the counter decrements from 0x00 to 0xFF. Note that the status bits in the
QDCSR are set coincident with the interrupt, and the interrupt (and status bits) are cleared
by reading the QDCSR.
Table F-5. Quadrature Decoder Registers
Register Name Mnemonic Address
Quad Decode Control/Status
Register
QDCSR 10010000 (0x90)
Bit Value Description
7
(rd-only)
0 Quadrature Decoder 2 did not increment from 0xFF.
1
Quadrature Decoder 2 incremented from 0xFF to
0x00. This bit is cleared by a read of this register.
6
(rd-only)
0 Quadrature Decoder 2 did not decrement from 0x00.
1
Quadrature Decoder 2 decremented from 0x00 to
0xFF. This bit is cleared by a read of this register
5 0 This bit always reads as zero.
4
(wr-only)
0 No effect on the Quadrature Decoder 2.
1
Reset Quadrature Decoder 2 to 0x00, without
causing an interrupt.
3
(rd-only)
0 Quadrature Decoder 1 did not increment from 0xFF.
1
Quadrature Decoder 1 incremented from 0xFF to
0x00. This bit is cleared by a read of this register.
2
(rd-only)
0 Quadrature Decoder 1 did not decrement from 0x00.
1
Quadrature Decoder 1 decremented from 0x00 to
0xFF. This bit is cleared by a read of this register.
1 0 This bit always reads as zero.
Bit Value Description
0
(wr-only)
0 No effect on the Quadrature Decoder 1.
1
Reset Quadrature Decoder 1 to 0x00, without
causing an interrupt.