YSI Incorporated
Model 5000/5100 Service Manual
26
SECTION 12 CIRCUIT DESCRIPTION
CPU
RESET
Reset to the CPU (U5) is supplied by a number of sources. The reset generator circuit monitors
the +5 supply line and pulls reset low when the voltage is out of limits. This function is provided
by U1, a MAX705.
The CPU itself will pull the RESET# pin low upon execution of a RST instruction. The RST
opcode is FFh, thus, execution of an erased section of ROM will cause a reset.
R3’s value has been established so that the MAX705 can pull the RESET# line low. While, on
the other hand, RESET# can go low while the MAX705’s output is high.
The reset signal is available at the expansion connector. The signal is bi-directional at this point.
If the line is held high, the reset pulse from the reset generator can be overridden. Similarly,
pulling this pin low will cause a reset.
CHIP SELECTS
CS0 - The CS0 chip select is active for the CCB fetches. This is used for the boot block chip
select and program FLASH, U16 for no wait states, de-multiplexed with a bus width of
16 bits.
CS1 - The CS1 chip select is used for off board RAM, U20 with no wait states, de-multiplexed
and a bus width of 8 bits.
CS2 - The CS2 chip select is reserved for expansion.
CS3 - The CS3 chip select is used for the display interface with three wait states, de-
multiplexed and a bus width of 8 bits.
CS4 - The CS4 chip select is used for latched output U6, with zero wait states, de-multiplexed
and a bus width of 8 bits.
CS5 - The CS5 chip select is used for the watchdog retrigger with zero wait states, de-
multiplexed and a bus width of 8 bits.
FLASH MEMORY
Models 5000/5100 have internal FLASH memory, IC16. When the VPPSHDN (P4.3) control
line is left floating or driven high all program operations, including boot and normal blocks, to
the chip are disabled. Pulling the VPPSHDN control line low will enable program operations to
all sections of the chip except the boot block. Either Q1 or U11 and its associated capacitors will
be included to supply the Vpp programming supply voltage that is necessary for the type of
FLASH populating each board.
SERIAL BUS
The Serial bus consists of a unidirectional clock line, bi-directional data line and unidirectional
chip select lines for each peripheral. A transfer is initiated when the 196 pulls one chip select
HIGH. The selected peripheral will then clock data in on the rising edge of the clock (data is
valid through the falling edge). After a command to read data from a peripheral the data line will
change direction. The 196 changes its data line to a high impedance input before the next
positive clock edge following a read command. The peripheral waits until after the positive
clock edge before driving data on the data line. Data from peripheral to master is latched on the
negative edge of the clock. In this fashion data is passed both directions with no unused clock
pulses while data direction changes. Data is always passed in 8 bit groups LSB first, there is no
