Pin
No.
Port Name
Function Name
Related Power Supply
Detail of Function
ON
OFF
I/O
Logic
I/O
Logic
42
IIO1_0/TXD8/N_SS2/
N_RTS2/N_CTS2/V/
TA1IN/P7_3
DK1_N_IPDET
I
L act
O
Low
Dock iPod detect
43
CLK2/V/TA1OUT/
P7_2
SR_PON
O
H act
O
Low
SIRIUS power s
u
pply control
44
MSCL/IEIN/ISRXD2/
OUTC2_2/IIO1_7/
STXD2/SCL2/RXD2/
TA0IN/TB5IN/P7_1
SR_MISO
I
Data
O
Low
SIRIUS reception data
45
TA0OUT/TXD2/
SDA2/SRXD2/
IIO1_6/OUTC2_0/
ISTXD2/IEOUT/
MSDA/P7_0
SR_MOSI
O
Data
O
Low
SIRIUS transmission data
46
TXD1/SDA1/SRXD1/
P6_7
232C_DBG_MOSI
O
Data
O
Low
RS-232C transmission data / Deb
u
g / E8a
47 P14_7
DSP_PON
O
H act
O
Low
DSP power s
u
pply
48
RXD1/SCL1/STXD1/
P6_6
232C_DBG_MISO
I
Data
O
Low
RS-232C reception data / Deb
u
g / E8a
49 P11_7
DAC_N_CS
O
L act
O
Low
DAC chip select (SW of V3071, FP DAC is D-FF)
50 CLK1/P6_5
DBG_SCK
I
Clock
O
Low
E8a
51
N_CTS1/N_RTS1/
N_SS1/OUTC2_1/
ISCLK2/P6_4
DBG_BUSY
O
O
Low
E8a
52
TXD0/SDA0/SRXD0/
P6_3
DSP_MOSI
O
Data
O
Low
DSP/DIR/DAC transmission data
53
TB2IN/RXD0/SCL0/
STXD0/P6_2
DSP_MISO
I
Data
I
---
DSP/DIR/DAC reception data
54 TB1IN/CLK0/P6_1
DSP_SCK
O
Clock
O
Low
DSP/DIR/DAC comm
u
nication clock
55
TB0IN/N_CTS0/N_
RTS0/N_SS0/P6_0
NCPU_N_INT
I
H act
O
Low
Network microprocessor interr
u
pt
56 P19_5
---
I
---
I
---
No
u
sed (+3.3DSP is applied, inp
u
t port setting)
57
D31/OUTC2_7/
P13_7
DSP1_N_RST
O
L act
O
Low
DSP1 reset
58
D30/OUTC2_1/
ISCLK2/P13_6
EX_SCK
O
Clock
O
Low
FL/EEPROM/ expansion IO comm
u
nication clock
59
D29/OUTC2_2/IS-
RXD2/IEIN/P13_5
EEP_MISO
I
Data
O
Low
EEPROM reception data
60
D28/OUTC2_0/
ISTXD2/IEOUT/
P13_4
EX_MOSI
O
Data
O
Low
FL/EEPROM/ expansion IO transmission data
61 P19_4
EEP_N_CS
O
L act
O
Low
EEPROM chip select
62
RDY/CS3/N_CTS7/
N_RTS7/P5_7
FPGA_N_CS
B
B
u
s
O
Low
External b
u
s FPGA chip select
63 ALE/CS2/RXD7/P5_6 DFF2_N_CS
B
B
u
s
O
Low
External b
u
s DFF2 chip select
64 HOLD/CLK7/P5_5
DBG_EPM
I
I
---
E8a
65
HLDA/CS1/TXD7/
P5_4
DFF1_N_CS
B
B
u
s
O
Low
External b
u
s DFF1 chip select
66
D27/OUTC2_3/
P13_3
---
O
Low
O
Low
No
u
sed
67 VSS
VSS
---
68
D26/OUTC2_6/
P13_2
DSP1_N_SPIRDY
I
L act
O
Low
DSP1 SPI ready
69 VCC
VCC
---
70
D25/OUTC2_5/
P13_1
DSP2_N_CS
O
L act
O
Low
DSP2 chip select
71
D24/OUTC2_4/
P13_0
DSP1_N_CS
O
L act
O
Low
DSP1 chip select
72 CLKOUT/BCLK/P5_3 NC(BCLK)
B
B
u
s
O
Low
External b
u
s
73 RD/P5_2
MCBUS_N_RD
B
B
u
s
O
Low
External b
u
s
74 WR1/BC1/P5_1
NC(BC1)
B
B
u
s
O
Low
External b
u
s
75 WR0/WR/P5_0
MCBUS_N_WR
B
B
u
s
I
---
External b
u
s
DBG_N_CE
I
I
---
E8a
76 D23/P12_7
MT_DA
O
H act
O
Low
M
u
te Digital A
u
dio
77 D22/P12_6
DIR_N_CS
O
L act
O
Low
DIR chip select
78 D21/P12_5
DIR_N_RST
O
L act
O
Low
DIR reset
67
RX-V771
RX-V771
Summary of Contents for RX-V771
Page 4: ...K model A model T model 4 RX V771 RX V771 ...
Page 5: ...B G F models L H models J model H model 5 RX V771 RX V771 ...
Page 6: ... REMOTE CONTROL PANELS RAV442 R A L H J models RAV443 T K B G F models 6 RX V771 RX V771 ...
Page 99: ...MAIN 2 Side B MAIN 6 Side B A B C D E F G H I J 1 2 3 4 5 6 7 RX V771 99 ...
Page 145: ... CONFIGURING THE SYSTEM SETTINGS RX V771 147 ...
Page 146: ... システム設定を変更する RX V771 148 ...
Page 147: ...MEMO 149 RX V771 RX V771 149 ...
Page 148: ...RX V771 ...
