RP-U200
RP-U200
17
IC417 : YSS928
AC3D3
120
11
118
117
116
11
114
113
112
111
110
109
108
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
78
77
80
79
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
13
107
14
106
15
105
16
104
17
103
18
102
19
101
20
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
21
12
11
10
9
8
7
6
5
4
3
2
1
34
35
36
37
38
39
40
33
32
31
30
29
28
27
26
25
24
23
22
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
YSS928
XO
XI
SELI1
SELI0
SELO
A
SELOB
TESTMS
TESTXEN
IPOR
T0
IPOR
T1
IPOR
T2
IPOR
T3
IPOR
T4
DDIN0
DDIN1
DDIN2
DDIN3
VSS
CPO
A
VDD
DIRPCO
DIRPR
O
A
VSS
TESTBRK
TESTR1
TESTR2
VDD1
SD
WCKI0
SDBCKI0
/SDBCK
O
IPOR
T8
IPOR
T9
IPOR
T10
IPOR
T11
SDIA
SDO
A2
SDO
A1
SDO
A0
SDIB3
SDIB2
RAMA9
RAMA3
RAMA4
SELI9
SELI10
SELI11
SELI12
SELI13
RAMA2
RAMA5
RAMA1
RAMA6
RAMA0
RAMA7
RAMA8
VDD1
VSS
RASN
RAMOEN
RAMWEN
CASN
RAMD15
RAMD14
RAMD13
RAMD12
RAMD11
RAMD10
RAMD9
RAMD8
VDD1
VSS
RAMD7
RAMD6
RAMD5
RAMD4
ZER
OBF0L
ZER
OBF0R
ZER
OBF1L
ZER
OBF1R
RAMD3
RAMD2
RAMD1
RAMD0
VDD2
VSS
OPORT7
OPORT6
OPORT5
OPORT4
OPORT3
OPORT2
OPORT1
OPORT0
ZEROBF2L
ZEROBF2R
ZEROBF3L
ZEROBF3R
VDD1
SDOB0
SDOB1
SDOB2
SDOB3
VSS
SDBCKI1
SDWCKI1
DBL/V
FS128/C
SYNC/U
ERR/BS
DIRMCK
DIRBCK
DIRWCK
DIRSDO
IPORT14
IPORT13
IPORT12
VDD2
VSS
SDIB0
SDIB1
RAMA10
RAMA11
VSS
VDD2
SELI8
SELI7
SELI6
SELI5
RAMA12
RAMA13
RAMA14
RAMA15
RAMA16
RAMA17
OVFB/END
ZEROFLG
VSS
NONPCM
DTSDATA
AC3DATA
MUTE
KARAOKE
VDD1
SURENC
CRC
/LOCK
DIRINT
/CS
SO
SI
SCK
/IC
IPINT
SELI4
VSS
SELI3
SELI2
TESTXI
TESTXO
VDD2
FS128/C
SYNC/U
DIRINT
DDIN0
DDIN1
DDIN2
DDIN3
ERR/BS
DBL/V
/LOCK
DIRPCO
DIRPR
O
DIRSDO
SDIA
SURENC
KARA
OKE
MUTE
CRC
A
C3D
A
T
A
DTSD
A
T
A
NONPCM ZER
OFLG
XI
XO
CPO
SDO
A0
SDO
A1
SDO
A2
SDIB0 SDIB1 SDIB2 SDIB3
RAND0
–
15
CASN RASN
RAMWEN RAMOEN
RAMA0
–
17
O
VFB/END
ZER
OBF3R
–
0L
SELOB
SELOA
SDBCKI1
SDWCKI1
SDOB0
SDOB1
SDOB2
SDOB3
DIRMCK
DIRBCK DIR
WCK
SDBCKI0 SD
WCKI0
/SDBCK
O
IPOR
T0
–
4
IPOR
T8
–
14
IPINT
/CS
SO
SI
SCK
OPOR
T0
–
7
SELI0
–
13
IPOR
T5
–
7
CMOD
UMOD
DDINSEL
BSMOD
VMOD
DIR
DIR
O
INTERF
A
C
E
SDIA
INTERF
A
C
E
SDO
A
INTERF
A
C
E
SDIB
INTERF
A
C
E
SUB DSP
MAIN DSP
A
C
-3/PR
O
LOGIC/DTS
DECODER
5
6
7
DBL
PLL
DIR CLOCK
(25MHz)
V
ERR
BS
SYNC
U
FS128
C
SDIASEL
SDIBSEL
SDIA
CKSEL
SDOB
INTERF
A
C
E
CRC
PLL
DSP CLOCK
(30MHz)
EXTERNAL
RAM
INTERFACE
OVFSEL
L, R
LS
, RS
C
, LFE
SDIBCKSEL
SDOBCKSEL
MICROPROCESSOR INTERFACE
CONTROL REGISTER
COEFFICIENT
PROGRAM
RAM
SELA SELB
CONTROL SIGNAL
MPLOAD
O
VFB
END
■
IC DATA