Yamaha PX10, Service Manual

Page: 20 / 148

20
PX10/PX8/PX5/PX3
PIN
NO.
I/O FUNCTION NAME
PIN
NO.
I/O FUNCTION NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
GPIO5
GPIO4
GPIO3
DVSS
GPIO2
GPIO1
GPIO0
PLLVDD
IC_N
PLLVSS
PLLVSS
XIN
XOUT
IOVDD
SCL
SDA
I/O
I/O
I/O
-
I
I
I
-
I
-
-
I
O
-
I
I/O
General-purpose I/O pins
GND
General-purpose I/O pins
PLL power supply
Hardware reset pin
PLL GND
Clock input pin
Clock output pin
Control interface power supply
I
2
C control bus clock input pin
I 2 C control bus data I/O pin
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
OPEN
DVSS
IRQ_N
DVDD18
GPIO11
TESTb
DVSS
OPEN
DVSS
GPIO10
GPIO9
GPIO8
IOVDD
GPI07
DVDD18
GPI06
-
-
O
-
I/O
I
-
-
-
I/O
I/O
I/O
-
I/O
-
I/O
Leave this pin open
GND
Interrupt request output pin to the host controller
Core power supply
General-purpose I/O pins
Test pin
GND
Leave this pin open
GND
General-purpose I/O pins
Control interface power supply
General-purpose I/O pins
Core power supply
General-purpose I/O pins
YSS952-QZE2A
(YE441A00)
DSP (SPR-2)
(Digital Signal Processor)
AUDIO: IC410
YDA177-VZ (YF978A00) DIGITAL POWER AMPLIFIER
AUDIO : IC601
PIN
NO.
I/O FUNCTION NAME
PIN
NO.
I/O FUNCTION NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
DVSS
XTALVSS
XO
XI
XTALGND
CLKINS
FSSELA0
FSSELA1
FSSELB0
FSSELB1
ADDRESS0
ADDRESS1
ZERODET
TEST
MSSEL
DGND
CLKOUT
CLKINB
DVSS
DVSS
SDA
SCL
MUTEIA_N
MUTEIB_N
PROTA_N
PROTB_N
CLIPA_N
CLIPB_N
IOVDD33
CURLB
CURHB
AMPTEMPB
VSENSEB
ISENSEB
VINTB
IINTB
AVDDB
AINB
VOUTB
VGNDB
AVSSB
INPB
INMB
AGNDB
-
-
O
Is
-
I
I
I
I
I
I
I
I
I
I
-
O
I
-
-
Is/OD
Is
AI
AI
OD
OD
OD
OD
-
AI
AI
AI
AI
AI
AI
AI
-
AI
AO
-
-
AI
AI
-
Digital block power supply DVSS(-5V)
XTAL power supply DVSS(-5V)
XTAL output
XTAL input
GND for XTAL
System clock for slave mode
A channel carrier clock switching pin
B channel carrier clock switching pin
I2C slave address setting
Zero crossing sensing function enable / disable setting
Test mode setting terminal (Internal specification)
Device master / slave setting pin
Digital block power supply GND (0V)
Clock output
Clock input for B channel
Digital block power supply P(-5V)
I2C data
I2C clock
A channel mute external control terminal
B channel mute external control terminal
A channel protection signal
B channel protection signal
A channel clip sensing flag signal
B channel clip sensing flag signal
External I2C host device power sensing P (3.3V)
B channel Low-side OCP sensing signal
B channel Hi-side OCP sensing signal
B channel heatsink temperature sensing terminal (thermistor)
B channel Output voltage sensing pin
B channel output current sensing pin
B channel Integral capacity connection for voltage monitor
B channel Integral capacity connection for current monitor
B channel Analog block power supply AVDD(+5V)
B channel input terminal
B channel electronic volume output terminal
power supply for B channel electronic volume GND(0V)
B channel analog block power supply AVSS(-5V)
B channel power amplifier input + terminal
B channel power amplifier input - terminal
B channel analog block power supply GND(0V)
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
OFFTB
LFB
MUTEB_N
OUTB
OUTBX
VREF
MBMNT
OUTAX
OUTA
MUTEA_N
LFA
OFFTA
AGNDA
INMA
INPA
AVSSA
VGNDA
VOUTA
AINA
AVDDA
PBMNT
IINTA
VINTA
ISENSEA
VSENSEA
AMPENBL
AMPTEMPA
CURHA
CURLA
PSTEMP
VOLA
VOLB
DGND
RECOV
PLENBL
PARAMSET
AI
AI
O
O
O
AO
AI
O
O
O
AI
AI
-
AI
AI
-
-
AO
AI
-
AI
AI
AI
AI
AI
I
AI
AI
AI
AI
AI
AI
-
I
I
I
(*1 connect to GNDB through a 0
Ω
resistor.)
FRQQHFWWR966%WKURXJKDѥ)FDSDFLWRU
(Capacitor :No Mount)
B channel Loop Filter capacitor connection terminal
B channel driver IC mute control terminal
B channel PWM output terminal
(Hi/Low by control for Hi-side signal)
B channel PWM output terminal
(Hi/Low by control for LoW-side signal)
Analog intermediate voltage (AVSS/2)
The final stage for the power supply (-200V) partial pressure signal
A channel PWM output terminal
(Hi/Low by control for LoW-side signal)
A channel PWM output terminal
(Hi/Low by control for Hi-side signal)
A channel driver IC mute control terminal
A channel Loop Filter capacitor connection terminal
(*1 connect to GNDA through a 0
Ω
resistor.)
FRQQHFWWR$966$WKURXJKDѥ)FDSDFLWRU
(Capacitor :No Mount)
A channel Analog block power supply GND(0V)
A channel power amplifier input + terminal
A channel power amplifier input - terminal
A channel analog block power supply AVSS(-5V)
A channel electronic volume connection terminal GND(0V)
A channel electronic volume connection terminal
A channel input terminal
A channel analog block power supply AVDD(+5V)
The final stage for the power supply (+200V) partial pressure signal
A channel Integral capacity for current monitor
A channel Integral capacity connection for voltage monitor
Output current sensing pin
Output voltage sensing pin
Start up timer terminal
A channel heatsink temperature sensing terminal (thermistor)
A channel Hi-side OCP sensing signal
A channel Low-side OCP sensing signal
Primary power source temperature (POSISTOR signal)
A channel volume terminal
B channel volume terminal
Digital block power supply GND(0V)
Automatic return function enable / disable setting
POWER LIMIT function enable / disable setting
Parameter input switching pin