82
RX-V2065/HTR-6295
RX-V2065/HTR-6295
Pin
No.
Port Name
Function
Name
(P.C.B.)
I/O
Detail of Function
P
o
w
erOn
Stb
y Thr
h
Standb
y
Stb
y Sleep
Sleep [MCU]
E8a,
ICP
1
TXD4
SCPU_MOSI
SO
O
O
O
[O]
Synchronous data output for SubCPU
2
CLK4
SCPU_SCK
SO
O
O
O
[O]
Synchronous clock output for SubCPU
P95/ANEX0/CLK4
3
P94
SCPU_CTS
SI
I
I
O
[O]
Input for transmission control for SubCPU (clear to send)
P94/DA1/TB4in/
CTS4/RTS4/SS4
4
DA0
AMP_LMT
DA
I
I
I
[I]
Limiter control output
P93/DA0/TB3in/
CTS3/RTS3/SS3
5
TXD3
XM_MOSI
SO
O
O
O
O
Asynchronous data output for XM
(U model)
P92/TB2in/TXD3/
SDA3/SRXD3/
OUTC20/IEout/
ISTXD2
P92
O
O
O
O
O
(C, R, T, K, A, L models)
TB2in
RDS_RDY
TMR
O
O
O
O
RDS READY input
6
RXD3
XM_MISO
SI
O
O
O
O
Asynchronous data input for XM
(U model)
P91/TB1in/RXD3/
SCL3/STXD3/IEin/
ISRXD2
P91
O
O
O
O
[O]
(C, R, T, K, A, L models)
RXD3
RDS_MISO
SI
O
O
O
[O]
Synchronous data input for RDS
(B, G, E, F model)
7
P90
XM_LINK
I
I
O
O
[O]
XM LINK detection
(U model)
P90/TB0in/CLK3
P90
O
O
O
O
[O]
(C, R, T, K, A, L models)
CLK3
RDS_SCK
SO
O
O
O
[O]
Synchronous clock output for RDS IC
Low level should stand by
(B, G, E, F model)
8
INT8
IPD_DET
IRQ
IRQ
IRQ
IRQ
[O]
iPod detection
Restriction of port: INT is high edge or low edge only
When inserting an iPod into the DOCK H –> L
P146/INT8
9
P145
DIR_N_INT
IRQ
I
O
O
[O]
DIR interrupt
Restriction of port: INT is high edge or low edge only
P145/INT7
10
P144
DSP_N_INT
IRQ
I
O
O
[O]
DA70Y interrupt
Restriction of port: INT is high edge or low edge only
P144/INT6
11
P143
XM_N_RST
O
O
O
O
O
XM reset
(U model)
P143/INPC17/
OUTC17
P143
O
O
O
O
O
(C, R, T, K, A, L models)
P143
RDS_N_RST
O
O
O
O
O
RDS reset
(B, G, E, F model)
12
P142
XM_REV
I
I
O
O
[O]
XM antenna revision detection
H: An compatibility antenna
(U model)
P142/INPC16/
OUTC16
P142
O
O
O
O
[O]
(C, R, T, K, A, B, G, E, F, L models)
13
P141
DIR_N_CS
CS
O
O
O
[O]
DIR chip select
P141/INPC15/
OUTC15
14
P140
DSP_N_RST
O
O
O
O
[O]
DA70Y reset
P140/INPC14/
OUTC14
15
BYTE
BYTE
MCU
MCU
MCU
MCU [MCU]
Switch of width of data bus input
When set to single chip mode: L (16 bit)
BYTE
16
CNVss
CNVss
MCU
MCU
MCU
MCU [MCU]
Processor mode select
Low: Single chip mode
High: To Flash included boot mode
To boot mode with hardware resetting of P50=H, P55=L, CNVss=H,
and a standard serial.
Input/output mode
CNVss
17
P87
DSP_N_CS
CS
O
O
O
[O]
DA70Y chip select
P87/Xcin
18
P86
DAC_N_CS
CS
O
O
O
[O]
DAC chip select
P86/Xcout
Summary of Contents for HTR-6295
Page 6: ...6 RX V2065 HTR 6295 RX V2065 HTR 6295 RX V2065 A model RX V2065 T model RX V2065 K model ...
Page 160: ...161 RX V2065 HTR 6295 RX V2065 HTR 6295 ADVANCED SETUP ...
Page 161: ...162 RX V2065 HTR 6295 RX V2065 HTR 6295 ...
Page 162: ...163 RX V2065 HTR 6295 RX V2065 HTR 6295 MEMO ...
Page 163: ...RX V2065 HTR 6295 ...
