Pin
No.
Port Name
Function Name
Related Power Supply
Detail of Function
ON
OFF
I/O
Logic
I/O
Logic
79 P19_3
DK1_AP
I
L act
I
---
iPod accessory power
80 P17_3
DK1_PON
O
H act
O
Low
Dock power s
u
pply
81 P17_2
UAW_PON
O
H act
O
Low
UAW power s
u
pply control
82 P17_1
NCPU_PON
O
H act
O
Low
NET/USB power s
u
pply
83 P17_0
NET_SEL_M
O
H NET
O
Low
Main USB/NET select
84 P19_2
NET_SEL_Z
O
H NET
O
Low
Zone USB/NET select
85
CS0/A23/TXD6/
SDA6/SRXD6/P4_7
FLASH_N_CS
O
L act
O
Low
External b
u
s Flash ROM chip select
86
CS1/A22/RXD6/
SCL6/STXD6/P4_6
A[22]
B
B
u
s
O
Low
External b
u
s
87 CS2/A21/CLK6/P4_5 A[21]
B
B
u
s
O
Low
External b
u
s
88
CS3/A20/N_CTS6/N_
RTS6/N_SS6/P4_4
A[20]
B
B
u
s
O
Low
External b
u
s
89
A19/TXD3/SDA3/
SRXD3/OUTC2_0/
ISTXD2/IEOUT/P4_3
A[19]
B
B
u
s
O
Low
External b
u
s
90 P11_6
---
O
Low
O
Low
Spare
91
A18/RXD3/SCL3/
STXD3/ISRXD2/IEIN/
P4_2
A[18]
B
B
u
s
O
Low
External b
u
s
92 P11_5
---
O
Low
O
Low
Spare
93 A17/CLK3/P4_1
A[17]
B
B
u
s
O
Low
External b
u
s
94
A16/N_CTS3/N_
RTS3/N_SS3/P4_0
A[16]
B
B
u
s
O
Low
External b
u
s
95 P16_7/TXD10
DK_MOSI
O
Data
O
Low
Dock UART transmission data
96 P16_6/RXD10
DK_MISO
I
Data
I
---
Dock UART reception data (3.3V logic inp
u
t)
97 P16_5/CLK10
R32C_N_INT
O
L act
O
Low
Interr
u
pt of R32C to Blackfin
98
P16_4/N_CTS10/N_
RTS10
BF_MT
I
H act
O
Low
M
u
te signal from Blackfin (NCPU_N_INT distinction
u
se)
99
A15/[A15/D15]/TA4IN/
U/P3_7
A[15]
B
B
u
s
O
Low
External b
u
s
100
A14/[A14/D14]/
TA4OUT/U/P3_6
A[14]
B
B
u
s
O
Low
External b
u
s
101
A13/[A13/D13]/TA2IN/
W/P3_5
A[13]
B
B
u
s
O
Low
External b
u
s
102
A12/[A12/D12]/
TA2OUT/W/P3_4
A[12]
B
B
u
s
O
Low
External b
u
s
103 P16_3/TXD9
NCPU_PIC_MISO
O
Data
O
Low
Network microprocessor SPI transmission data
104 P16_2/RXD9
NCPU_PIC_MOSI
I
Data
O
Low
Network microprocessor SPI reception data
105 P16_1/CLK9
NCPU_PIC_SCK
I
Clock
O
Low
Network microprocessor SPI comm
u
nication clock
106
P16_0/N_CTS9/N_
RTS9
NCPU_N_RST
O
L act
O
Low
Network microprocessor reset
107
A11/[A11/D11]/TA1IN/
V/P3_3
A[11]
B
B
u
s
O
Low
External b
u
s
108
A10/[A10/D10]/
TA1OUT/V/P3_2
A[10]
B
B
u
s
O
Low
External b
u
s
109
A9/[A9/D9]/TA3OUT/
UD0B/UD1B/P3_1
A[9]
B
B
u
s
O
Low
External b
u
s
110 D20/P12_4
---
O
Low
O
Low
Spare
111
D19/N_CTS6/N_
RTS6/N_SS6/P12_3
---
O
Low
O
Low
Spare
112
D18/RXD6/SCL6/
STXD6/P12_2
---
O
Low
O
Low
Spare (After FPGA Config, I2C is possible)
113 D17/CLK6/P12_1
FPGA_SCK
O
Clock
O
Low
FPGA clock (at Boot)
114
D16/TXD6/SDA6/
SRXD6/P12_0
FPGA_MOSI
O
Data
O
Low
FPGA transmission data (at Boot)
115 VCC
VCC
---
116
A8/[A8/D8]/TA0OUT/
UD0A/UD1A/P3_0
A[8]
B
B
u
s
O
Low
External b
u
s
117 VSS
VSS
---
118
A7/[A7/D7]/AN2_7/
P2_7/TXD10
A[7]
B
B
u
s
O
Low
External b
u
s
119
A6/[A6/D6]/AN2_6/
P2_6/RXD10
A[6]
B
B
u
s
O
Low
External b
u
s
120
A5/[A5/D5]/AN2_5/
P2_5/CLK10
A[5]
B
B
u
s
O
Low
External b
u
s
74
RX-V671/HTR-6064/RX-A710
RX-V671/HTR-6064/
RX-A71
0
DRAFT
