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HTR-5890

36

IC512: D601A002PYP180 (DSP P.C.B)
Decoder

IC512: D601A002PYP180 (DSP P.C.B)
Decoder

Pin Multiple

xing

EMIF32

L1P Cache

Direct Mapped
4K Bytes Total

Digital Signal Processors

L1D Cache

2-Way Set

Associative

4K Bytes Total

Clock Generator,

Oscillator and PLL

x4 through x25 Multipliers

/1 through /32 Dividers

Power-Down

Logic

Instruction Fetch

Instruction Dispatch

Instruction Decode

Data Path B

Data Path A

B Register File

Control

Registers

C67x

TM

 CPU

Control

Logic

In-Circuit

Emulation

Interrupt

Control

Test

A Register File

.L1t

McASP1

McASP0

McBSP1

McBSP0

I2C1

I2C0

Timer 1

Timer 0

.S1t .M1t .D1

.D2 .M2t .S2t .L2t

GP1

GP0

HPI16

Enhanced

DMA

Controller

(16 channel)

L2 Cache/

Memory
4 Banks

64K Bytes

Total

(4-Way)

L2

Memory

DA610:

192K Bytes

DA601:

64K Bytes

R2 ROM

512K
Bytes

Total

No.

Name

I/O

Function

1

GP0[4]/(EXT̲INT4)

IOZ

General purpose I/O0 port 4

2

GP0[6]/(EXT̲INT6)

IOZ

General purpose I/O0 port 6

3

CVDD

S

1.2V power supply

4

VSS

GND

Ground

5

DVDD

S

3.3V power supply

6

GP0[5]/(EXT̲INT5)

IOZ

General purpose I/O0 port 5

7

GP0[7]/(EXT̲INT7)

IOZ

General purpose I/O0 port 7

8

CLKS1

I

McBSP1 external clock source

9

DVDD

S

3.3V power supply

10

VSS

GND

Ground

11

CVDD

S

1.2V power supply

12

TINP1/AHCLKX0

I

Timer 1 Input

13

TOUT1/AXRO[4]/AXR1[11]

O

Timer 1 Output

14

CVDD

S

1.2V power supply

15

VSS

GND

Ground

16

CLKX0/ACLKX0

IOZ

McASP0 Transmission BCLK

17

TINP0/AXRO[3]/AXR1[12]

I

Timer 0 Input

18

TOUT0/AXRO[2]/AXR1[13]

O

Timer 0 Output

19

ACLKR0

IOZ

McASP0 Reception BCLK

20

AXRO[1]

IOZ

McASP0 Transmission/reception data 1

21

AFSX0

IOZ

McASP0 Transmission LRCLK

22

CVDD

S

1.2V power supply

23

VSS

GND

Ground

24

AFSR0

IOZ

McASP0 Reception LRCLK

25

DVDD

S

3.3V power supply

26

VSS

GND

Ground

27

AXRO[0]

IOZ

McASP0 Transmission/reception data 0

28

AHCLKR0

I

McASP0 Reception MCLK

29

CVDD

S

1.2V power supply

30

VSS

GND

Ground

31

FSX1

IOZ

McBSP1 Transmission Frame Sync (Input in SPI slave state)

32

DX1

O/Z

McBSP1 Transmission data

33

CLKX1

IOZ

McBSP1 Transmission clock (Input in SPI slave state)

34

VSS

GND

Ground

35

CVDD

S

1.2V power supply

36

CLKR1

IOZ

McBSP1 Reception clock

37

DR1

I

McBSP1 Reception data

38

FSR1

IOZ

McBSP1 Reception Frame Sync

39

VSS

GND

Ground

40

CVDD

S

1.2V power supply

No.

Name

I/O

Function

41

SCL0

IOZ

12C0 clock

42

SDA0

IOZ

12C0 data

43

CVDD

S

1.2V power supply

44

DVDD

S

3.3V power supply

45

VSS

GND

Ground

46

CVDD

S

1.2V power supply

47

DVDD

S

3.3V power supply

48

VSS

GND

Ground

49

VSS

GND

Ground

50

CVDD

S

1.2V power supply

51

CVDD

S

1.2V power supply

52

VSS

GND

Ground

53

CVDD

S

1.2V power supply

54

VSS

GND

Ground

55

DVDD

S

3.3v power supply

56

ARDY

I

Asynchronous RAM Ready input

57

/CE3

O/Z

For external memory area, Enable 3

58

DVDD

S

3.3V power supply

59

VSS

GND

Ground

60

CVDD

S

1.2V power supply

61

/CE2

O/Z

For external memory area, Enable 2

62

EA2

O/Z

For external memory, Address 2

63

EA3

O/Z

For external memory, Address 3

64

EA4

O/Z

For external memory, Address 4

65

DVDD

S

3.3V power supply

66

VSS

GND

Ground

67

CVDD

S

1.2v power supply

68

EA5

O/Z

For external memory, Address 5

69

EA6

O/Z

For external memory, Address 6

70

EA7

O/Z

For external memory, Address 7

71

EA8

O/Z

For external memory, Address 8

72

DVDD

S

3.3V power supply

73

VSS

GND

Ground

74

EA9

O/Z

For external memory, Address 9

75

/SDRAS

O/Z

Asynchronous RAM OE / SDRAM RAS / SBS RAM OE

76

EA10

O/Z

For external memory, Address 10

77

ECLKOUT

O/Z

Clock output for EMIF

78

ECLKIN

I

Clock input for EMIF

79

/SDCAS

O/Z

Asynchronous RAM RE / SDRAM CAS / SBSRAM ADS

80

CVDD

S

1.2V power supply

81

VSS

GND

Ground

82

CLKOUT2/GP0[2]

O/Z

Half clock output of device Speed

83

/SDWE

O/Z

Asynchronous RAM WE / SDRAM WE / SBSRAM WE

84

DVDD

S

3.3V power supply

85

VSS

GND

Ground

86

EA11

O/Z

For external memory, Address 11

87

DVDD

S

3.3V power supply

88

VSS

GND

Ground

89

CVDD

S

1.2V power supply

90

EA14

O/Z

For external memory, Address 14

91

EA13

O/Z

For external memory, Address 13

92

EA16

O/Z

For external memory, Address 16

93

EA12

O/Z

For external memory, Address 12

94

EA15

O/Z

For external memory, Address 15

95

EA18

O/Z

For external memory, Address 18

96

CVDD

S

1.2V power supply

97

VSS

GND

Ground

98

DVDD

S

3.3V power supply

*

No service part

avilable.

Summary of Contents for htr-5890

Page 1: ...curate and applicable to the unit s indicated on the cover The research engineering and service departments of YAMAHA are continually striving to improve YAMAHA products Modifications are therefore inevitable and specifications are subject to change without notice or obligation to retrofit Should any discrepancy appear to exist please contact the distributor s Service Division WARNING Static disch...

Page 2: ...ce should be equivalent to 1500 ohms shunted by 0 15µF CAUTION F1 F2 FOR CONTINUED PROTECTION AGAINST RISK OF FIRE REPLACE ONLY WITH SAME TYPE 10A 125V FUSE CAUTION F1 F2 REPLACE WITH SAME TYPE 10A 125V FUSE ATTENTION F1 F2 UTILISER UN FUSIBLE DE RECHANGE DE MEME TYPE DE 10A 125V Leakage current must not exceed 0 5mA Be sure to test for leakage with the AC plug in both polarities About Lead Free S...

Page 3: ...HTR 5890 3 HTR 5890 FRONT PANEL REMOTE CONTROL PANEL ...

Page 4: ...HTR 5890 4 HTR 5890 A model REAR PANELS U C models ...

Page 5: ...ME 1 0 5 0 0 1 1 0 5 0 0 1 1 0 5 0 0 1 s REV DLY 0 250 1 0 250 1 0 250 1 ms REV LEVEL 0 100 1 0 100 1 0 100 1 PANORAMA OFF OFF ON DIMENSION 0 STD 3 3 1 CT WIDTH 0 0 7 1 C IMAGE 0 0 5 0 1 DIALG LIFT 0 5 1 0 5 1 0 5 1 PLⅡ PLⅡx PLⅡ PLⅡx PLⅡ PLⅡx DIMENSIONS 7ch Stereo Parameter Unit CT LEVEL 0 100 1 SL LEVEL 0 100 1 SR LEVEL 0 100 1 SB LEVEL 0 100 1 PL LEVEL 0 100 1 PR LEVEL 0 100 1 Video Section Vide...

Page 6: ... feet 1 0 to 80 feet 0 5 feet step feet SB L 7 0 feet 1 0 to 80 feet 0 5 feet step feet SB R 7 0 feet 1 0 to 80 feet 0 5 feet step feet SWFR 10 0 feet 1 0 to 80 feet 0 5 feet step feet PRESENCE L 10 0 feet 1 0 to 80 feet 0 5 feet step feet PRESENCE R 10 0 feet 1 0 to 80 feet 0 5 feet step D GRAPHIC EQ Channel L L R CT SR L R SB L R PRES L R 63 Hz 0 dB 6 dB 0 5 dB step 160 Hz 0 dB 6 dB 0 5 dB step ...

Page 7: ...UT SET 1 6ch 8ch 6ch 6 ch 8 ch 2 8CH INPUT FRONT DVD 3 CENTER to CENTER CENTER FRONT 4 SWFR to SWFR SWFR FRONT 5 SL SR SL SR SL SR FRONT 4 OPTION MENU A DISPLAY SET DIMMER 0 4 to 0 1 step OSD SHIFT 0 0 5 1 step GRAY BACK AUTO AUTO OFF V CONV ON OFF ON CMPNT OSD ON OFF ON B MEMORY GUARD OFF OFF ON C PARAM INI PARAM INIT D SP IMP SET 8 ohms 8 ohms 6 ohms E ZONE SET SP B SET FRONT FRONT ZONE B F ZONE...

Page 8: ...SION P C B 0 VIDEO 8 P C B A VIDEO 7 P C B B VIDEO 3 P C B C VIDEO 5 P C B D VIDEO 6 P C B E VIDEO 2 P C B F VIDEO 1 P C B G MAIN 2 P C B H DSP P C B I FUNCTION P C B J MAIN 4 P C B K POWER 1 P C B L POWER 3 P C B M OPERATION 7 P C B N OPERATION 5 P C B O OPERATION 2 P C B P OPERATION 4 P C B Q OPERATION 8 P C B R OPERATION 6 P C B S OPERATION 1 P C B T OPERATION 3 P C B Q S R T INTERNAL VIEW ...

Page 9: ...s numbered Disconnect the power cable from the AC outlet Fig 1 1 Removal of Top Cover a Remove 2 screws 1 4 screws 2 and 5 screws 3 Fig 1 b Slide the Top Cover rearward to remove it Fig 1 2 Removal of Front Panel Unit a Remove 9 screws 4 and then slide the Front Panel Unit forward Fig 1 b Remove CB25 CB505 CB509 CB512 CB861 CB863 and then remove the Front Panel Unit Fig 2 Fig 2 ...

Page 10: ...nd then remove the Bracket Fig 4 c Remove 1 screw 7 Fig 4 d Remove 8 screws 8 Fig 5 e Remove CB501 CB503 CB505 Fig 3 f Remove the DSP P C B and Shield Case upward Fig 4 4 Removal of VIDEO 2 P C B a Remove 1 screw 9 Fig 4 b Remove CB554 CB555 and CB558 Fig 3 c Remove the VIDEO 2 P C B which is connected directly to the lower P C B with connectors Fig 4 CB503 CB501 CB505 CB504 CB555 CB558 CB554 Fig ...

Page 11: ...2 OPERATION 1 P C B CB852 MF115500 15P 500mm When connecting the flat cable use care for the polarity 5 Removal of VIDEO 1 3 5 8 FUNCTION CONVERSION P C B s and Tuner a Remove 26 screws 0 Fig 5 b Remove VIDEO 1 3 5 8 FUNCTION CONVERSION P C B s and Tuner FUNCTION P C B VIDEO 2 P C B VIDEO 3 P C B CONVERSION P C B VIDEO 5 P C B VIDEO 1 P C B Ground Point Ground Point Earth lead wire In this unit th...

Page 12: ...vets D and then remove the Duct Fig 8 b Remove 4 screws E and 4 screws F Fig 8 c Remove the Amp Unit Fig 8 When checking the Amp Unit Put the Amp Unit together with the heat sink upright on the art base and check them Fig 9 Reconnect all cables connectors that have been disconnected Be sure to use the extension cable for servicing for the following section FUNCTION P C B CB507 POWER 1 P C B CB22 M...

Page 13: ...below 3 Turn on the power to the unit 4 To connect the line click the CONNECT button or the COM menu then click the CONNECT After connecting the Connected message is displayed in the status bar 5 Click the File Change button and then select the file to be loaded To start loading click the Program Macro button CAUTION Never disconnect the power cable of the unit while loading the firmware or the fl...

Page 14: ...OUND LR MUTE 7 SURROUND LR NONE 6 EXTERNAL INPUT 1 6CH INPUT_6OHMS 2 6CH INPUT_8OHMS 3 8CH INPUT_6OHMS 4 8CH INPUT_8OHMS 7 MIC CHECK MIC CHECK 8 EFFECT OFF 1 VFD CHECK Initial display DISPLAY CHECK 2 VFD DISP OFF All segments OFF 3 VFD DISP ALL All segments ON 100 4 VFD DIMMER All segments ON 50 5 CHECKED PATTERN ON in lattice 9 MANUAL TEST 1 TEST ALL 2 TEST FRONT L 3 TEST CENTER 4 TEST FRONT R 5 ...

Page 15: ...5 Byte 4 CS 2 5 Byte 5 CS 3 5 Byte 6 CS 4 5 Byte 7 CS 5 4 Byte 8 BS1 5 Byte 9 BS2 5 Byte 10 BS3 5 Byte 11 BS4 5 Byte 12 BS5 5 Byte 13 BS6 5 Byte 14 BS7 2 Byte 15 TI1 5 Byte 16 TI2 1 Byte 17 MTT 5 Byte 15 DSP RAM CHECK 1 YSS930 BUS CHECK 2 SECOND DECODER BUS CHECK 16 PROTECTION SET Not applied to this model 17 SOFT SW 1 SW MODE 2 MODEL SETTING 3 TUNER DESTINATION 4 TUNER EXIST 5 RDS EXIST 6 ZONE 2 ...

Page 16: ...he STANDBY ON key of the main unit or the STANDBY key of the remote controller Cause An excessive current flowed through the power amplifier Turning on the power without correcting the abnormality will cause the protection function to work immediately and the power supply will instantly be shut off Note Applying the power to a unit without correcting the abnormality can be dangerous and cause addi...

Page 17: ...of the startup screen appears on the superimposed screen and the function at work is indicated on the FL indicator The contents displayed during the function operation are described in the later section on details of functions History of protection function When the protection function has worked its history is stored in memory with a backup Even if no abnormality is noted while servicing the unit...

Page 18: ... the input mode key of the main unit Details of DIAG menu With full bit output specified in some modes it is possible to execute 0dBFS output without head margin in each channel 1 DA601 YSS930 This function is for YSS930 only Main DSP of YSS930 is selected for FRONT output Using the sub menu it is possible to select 0dB output level or full bit output YSS 0dB The signal is output including the hea...

Page 19: ...380 AD L R SBL SBR SWL SWR ReL ReR L R SL SR SL SR DIR L R CL CR PL PR SBL SBR or PL PR SWL SWR CL CR PL PR L R L R L R 4Mbit DRAM DA601 YSS930 ANALOG Shaded items not used in this example 2 BYPASS ANALOG BYPASS Reference data INPUT DVD ANALOG SUBWOOFER 50Hz Others 1kHz Input level Volume SPEAKER OUTPUT SUBWOOFER FRONT L R CENTER SURROUND L R SURROUND BACK OUTPUT Both ch 20 dBm 6 5 dB 13 5 dBm 13 ...

Page 20: ...ASS Reference data INPUT DVD ANALOG SUBWOOFER 50Hz Others 1kHz ANALOG BYPASS DSP BYPASS ANALOG 4Mbit DRAM SBL SBR C LFE SL SR TI DA601 YSS930 D1 YSS930 D0 LC89057 Analog Digital A D DIR DECODE DSP POST PROCESSING DSP POST PROCESSING DSP AK5380 AD L R SBL SBR SWL SWR ReL ReR L R SL SR SL SR CL CR PL PR SBL SBR or PL PR SWL SWR CL CR PL PR L R L R L R DIR L R Shaded items not used in this example DS...

Page 21: ...P POST PROCESSING DSP AK5380 AD L R SBL SBR SWL SWR ReL ReR L R SL SR SL SR DIR L R CL CR PL PR SBL SBR or PL PR SWL SWR CL CR PL PR L R L R L R 4Mbit DRAM POST PROCESSING DSP RAM THROUGH ANALOG Shaded items not used in this example Input level Volume SPEAKER OUTPUT SUBWOOFER FRONT L R CENTER SURROUND L R SURROUND BACK OUTPUT Both ch 20 dBm 6 5 dB 13 5 dBm 13 5 dBm 13 5 dBm 13 5 dBm 7 0 dBm Input ...

Page 22: ...CODE DSP POST PROCESSING DSP AK5380 AD L R SBL SBR SWL SWR ReL ReR L R SL SR SL SR DIR L R CL CR PL PR SBL SBR or PL PR SWL SWR CL CR PL PR L R L R L R 4Mbit DRAM POST PROCESSING DSP PRO LOGIC NEO 6 ANALOG Shaded items not used in this example Neo 6 Reference data INPUT DVD ANALOG SUBWOOFER 50Hz Others 1kHz Input level Volume SPEAKER OUTPUT SUBWOOFER FRONT L R CENTER SURROUND L R SURROUND BACK OUT...

Page 23: ...E NONE LARGE LARGE SWFR 3 LFE BASS FRONT SMALL SMALL LARGE MAIN 4 PRESS MIX 5CH LARGE LARGE LARGE SWFR 5 SURROUND BACK MUTE LARGE LARGE LARGE SWFR 6 SURROUND MUTE LARGE LARGE LARGE SWFR 7 SURROUND NONE LARGE NONE LARGE SWFR NONE This mode is used with no center speaker The center content is reduced by 3dB and distributed to FRONT L R Sub menu Input level Volume SPEAKER OUTPUT SUBWOOFER FRONT L R C...

Page 24: ... 0 dBm 3 8CH_INPUT_6ohms Both ch 20 dBm 6 5 dB 13 5 dBm 13 5 dBm 13 5 dBm 13 5 dBm 1 0 dBm 4 8CH_INPUT_8ohms Both ch 20 dBm 6 5 dB 13 5 dBm 13 5 dBm 13 5 dBm 13 5 dBm 1 0 dBm 6 EXTERNAL INPUT It is possible to select the 6ch 8ch input and 6_ 8_ by using the SUB menu Reference data INPUT MULTI CH INPUT SUBWOOFER 50Hz Others 1kHz 7 MIC CHECK The signals input through the microphone are output via A ...

Page 25: ...he second row from the top are shorted 8 EFFECT OFF DISPLAY CHECK This program is used to check the FL display section The display condition varies as shown below according to the sub menu operation The signals are processed using EFFECT OFF The L R signal is output using ANALOG MAIN BYPASS The video signal internal external synchronization switching is controlled by the microprocessor When the in...

Page 26: ...r the test command is transmitted RxD RTS CTS TxD 1 2 3 6 7 8 9 4 5 9 MANUAL TEST The noise generator with a built in DSP outputs the test noise through the channels specified by the sub menu The noise frequency for LFE is 35 to 250 Hz Other than that the center frequency is 800Hz TEST ALL TEST FRONT L TEST CENTER TEST FRONT R TEST SURROUND R TEST SURROUND BACK R Noise is output from all channels ...

Page 27: ... 50 2 90 1 90 10 3 95 1 95 10 A C E 4 98 1 98 10 5 107 9 108 00 6 88 1 88 10 7 106 1 106 10 8 107 9 108 00 STATION AM FACTORY PRESET DATA kHz PAGE NO U C A 1 630 630 2 1080 1080 3 1440 1440 B D 4 530 531 5 1710 1611 6 900 900 7 1350 1350 8 1400 1404 PRESET STATIONS 12 AD DATA CHECK FAN TEST This menu is used to display the A D conversion value of the main CPU which detects panel keys of the main u...

Page 28: ...XT8CH INPUT Other than those LC1 L LC1 L 157 on the above LC2 L LC2 H 163 K0 K1 Panel key of main unit A D of the key fails to function properly when the standard value is deviated by 4 In this case check the constant of partial pressure resistor solder condition etc Refer to table below Reference voltage 5V 100 Display K0 K1 00 2 PRESET TUNING 10 2 PRESET TUNING SPEAKERS A 20 2 PRESET TUNING SPEA...

Page 29: ...4 IF STATUS Input function status Using the sub menu the status data is displayed one after another in the hexadecimal notation During signal processing the status before execution of this menu is maintained Numeric values in the figure example are for reference 1st byte Digital input output setting value Upper 4 bits REC OUT selected lower 4 bits INPUT selected IS1 2 Internal status Indicates the...

Page 30: ...ag 60 AAC C0 Dolby Digital C1 D D Karaoke C4 D D 6 1 D D EX Display 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D Audio Code MULTI MONO 1 1 1 0 2 0 3 0 2 1 3 1 2 2 3 2 2 3 3 3 OVER 6 1 MULTI PCE Unknown 5th byte Signal processing status information 2 With digital signals other than 32kHz 44 1kHz and 48kHz through processing method is used for reproducible signals bit7 MUTE request bit3 bit6 Red dts fl...

Page 31: ...d possibility is that there is a defective part or poor connection of the microprocessor DA601 SDRAM NoEr Booting of DA601 has been completed properly 17 SOFT SW This menu is used to switch the function settings on P C B through the software so as to activate the product The operation mode can be changed by selecting the sub menu and then using the STRAIGHT key With SOFT selected for the SW mode t...

Page 32: ... mode Type 0 Type 1 Model type 0 0 HTR 5890 V1500 1 Model type Version Release 1 figure Main 2 figures DSP 2 figures Communication 1 figure Boot manufacturer 1 figure Boot 232C 1 figure OPE DSP Version Main 2 figures DSP 2 figures Checksum A All area P Program area Checksum 2 Boot 232C M Boot manufacturer Check of port setting for judging microprocessor function Display of AAC function detection p...

Page 33: ... Lch R320 FRONT Rch R325 CENTER R326 SURROUND Lch R327 SURROUND Rch R321 SURROUND BACK Lch R322 SURROUND BACK Rch are between 0 1mV and 10 0mV If it exceeds 10 0mV open cutoff R291 FRONT Lch R292 FRONT Rch R295 CENTER R296 SURROUND Lch R297 SURROUND Rch R293 SURROUND BACK Lch R294 SURROUND BACK Rch and reconfirm the voltage Attention If the idle current exceeds 10 0mV after an amplifier repair fir...

Page 34: ...No 65 F2 64 NX 63 NP 62 NP 61 P37 60 P36 59 P35 58 P34 57 P33 56 P32 55 P31 54 P30 53 P29 52 P28 51 P27 50 P26 49 P25 48 P24 47 P23 46 P22 45 P21 44 P20 43 P19 42 P18 41 P17 40 P16 39 P15 38 P14 37 P13 33 P9 32 P8 31 P7 30 P6 29 P5 28 P4 27 P3 26 P2 25 P1 24 NC 23 NC 22 NC 21 17G 20 16G 19 15G 18 14G 17 13G 16 12G 15 11G 14 10G 13 9G 12 8G 11 7G 10 6G 9 5G 8 4G 7 3G 6 2G 5 1G 4 NP 3 NP 36 P12 35 P...

Page 35: ...ble digital data Validity flag input pin for modulation 10 RX6 UI Is TTL compatible digital data User data input pin for modulation 11 DVDD PLL digital power supply 12 DGND PLL digital GND 13 LPF O PLL loop filter connection pin 14 ACDD PLL analog power supply 15 AGND PLL analog GND 16 RMCK O R system clock output pin 256fs 512fs XIN VCO 17 RBCK O I R bit clock input output pin 18 DGND Digital GND...

Page 36: ...k Input in SPI slave state 34 VSS GND Ground 35 CVDD S 1 2V power supply 36 CLKR1 IOZ McBSP1 Reception clock 37 DR1 I McBSP1 Reception data 38 FSR1 IOZ McBSP1 Reception Frame Sync 39 VSS GND Ground 40 CVDD S 1 2V power supply No Name I O Function 41 SCL0 IOZ 12C0 clock 42 SDA0 IOZ 12C0 data 43 CVDD S 1 2V power supply 44 DVDD S 3 3V power supply 45 VSS GND Ground 46 CVDD S 1 2V power supply 47 DVD...

Page 37: ...ion data 4 148 VSS GND Ground 149 CVDD S 1 2V power supply 150 AXR1 5 IOZ McASP1 transmission reception data 5 151 AXR1 6 IOZ McASP1 transmission reception data 6 152 AXRO 8 AXR1 7 IOZ McASP1 transmission reception data 7 153 ACLKX1 IOZ McASP1 transmission BCLK 154 AMUTE1 OZ McASP1 MUTE output 155 AFSX1 IOZ McASP1 transmission LRCLK 156 GP0 0 IOZ General purpose I O0 port 0 SPI ready signal output...

Page 38: ...Rch zero flag output terminal input output terminal for branching program conditions 12 AVSS Analog ground terminal for PLL 13 CPO A Terminal for connecting PLL filter 14 AVDD 2 5V digital power supply for PLL 15 VDD1 3 3V digital power supply for input output terminal 16 NC Unconnected 17 IOPORT8 I O General purpose input output terminal SD04 Lch zero flag output terminal 18 IOPORT9 I O General p...

Page 39: ...nal memory 73 RAMA9 O Address output terminal 9 for external memory 74 RAMA10 O Address output terminal 10 for external memory 75 VDD2 2 5V digital power supply for internal circuit 76 VSS Digital ground terminal 77 RAMA11 O Address output terminal 11 for external memory 78 RAMA12 O Address output terminal 12 for external memory 79 RAMA13 O Address output terminal 13 for external memory 80 RAMA14 ...

Page 40: ... SO O OL OL 2 P95 ANEX0 CLK4 CLK4 RTS 232C RTS YDC clock SCK I O OL OL 3 P94 DA1 TB4in CTS4 RTS4 SS4 P94 CTS 232C CTS I I I OL 4 P93 DA0 TB3in CTS3 RTS3 SS3 DA0 FAN Fan control DA O I I OL 5 P92 TB2in TxD3 SDA3 SRxD3 TxD3 SDTN None audio TX data SO SO OL OL 6 P91 TB1in RxD3 SCL3 STxD3 RxD3 RXRDS RDS RX data Freq data R ver SI SI I OL 7 P90 TB0in CLK3 CLK3 SCKN None audio serial clock SCK SCK OL OL...

Page 41: ... D15 D15 External ROM data 103 P16 D14 INT4 D14 D14 External ROM data 104 P15 D13 INT3 D13 D13 External ROM data 105 P14 D12 D12 D12 External ROM data 106 P13 D11 D11 D11 External ROM data 107 P12 D10 D10 D10 External ROM data 108 P11 D9 D9 D9 External ROM data 109 P10 D8 D8 D8 External ROM data 110 P07 D7 D7 D7 External ROM data 111 P06 D6 D6 D6 External ROM data 112 P05 D5 D5 D5 External ROM dat...

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