Yamaha HTR-5065, Service Manual

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NAND-Flash Interface
Ethernet MAC-Phy Interface (MII)
Pin No. Function Name I/O MII RMII SMII
U14 MIIDIO I/O Management data Management data
V14 MIIMDC O Management clock Management clock
V13 MIIRXD[3] I RxD 3 RxD 1
U13 MIIRXD[2] I RxD 2 RxD 0
V12 MIIRXD[1] I RxD 1 Rx-Sync
U12 MIIRXD[0] I RxD 0 RxD
T12 MIIRXCLK I Receive clock Receive clock
R13 MIIRXER I Receive error Receive error
T14 MIIRXDV I Receive data valid Carrier sense/data valid
V11 MIITXD[3] O TxD 3 TxD 1
U11 MIITXD[2] O TxD 2 TxD 0
V10 MIITXD[1] O TxD 1 Tx-Sync
U10 MIITXD[0] O TxD 0 TxD
R12 MIITXCLK I Transmit clock Transmit clock
T11 MIITXER O Transmit error
R11 MIITXEN O Transmit data enable Transmit data enable
T13 MIICOL I MII ethernet collision
R14 MIICRS I MII carrier sense
V15 MIIPHYCLK O 25.000 MHz clock 50.000 MHz clock 125.000 MHz clock
Pin No. Function Name I/O Detail of Function
T17
T16
T15
R17
FD[7:0] I/O Bi-directional data b u s.
R16
R15
P16
P15
V18 FALE O Address latch enable; p u ll- u p/down defines boot mode.
U16 FCLE O Command latch enable; p u ll- u p/down defines boot mode.
U15 NFCE0 O Chip-enable, low-active.
U18 NFRB I Ready/b u sy. NAND flash is b u sy when NFRB is low.
V17 NFRE O Read enable, low-active.
U17 NFWE O Write enable, low-active.
V16 NFWP O Write protect, low-active.
Pin No. Function Name I/O Detail of Function
H18 Chip select signals. The active memory range for NCS[n] (active low) can be config u red.
J17 • NCS[0] s u pports SRAM, can be u sed for booting.
J16 NCS[3:0] O • NCS[1] s u pports SDRAM or SRAM.
J15 • NCS[2] s u pports SRAM.
• NCS[3] s u pports SRAM.
K17 NOE O O u tp u t enable, asserted (low) for read operations.
K16 NWE O Write enable, asserted (low) for write operations.
K18 NWAIT I
External wait line. If NWAIT is asserted, memory access will be stalled. Can be config u red as either low-
active (defa u lt) or high-active.
K15 MEMCLK O SDRAM system clock.
J18 MEMCKE O SDRAM clock enable.
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RX-V573/HTR-5065
RX-V573/HTR-5065