Yamaha HTR-5065, Service Manual

Page: 58 / 134

Control Pins
Configuration Pins
CEC Pins
Pin
No.
Function Name Type I/O Detail of Function
Local config u ration/stat u s I2C clock.
66 CSCL
Schmitt Open drain 5
V tolerant
Inp u t
Chip config u ration/stat u s is accessed via this I2C port. This pin is tr u e open
drain, so it does not p u ll to gro u nd if power is not applied.
Local config u ration/stat u s I2C data.
67 CSDA
LVTTL Schmitt Open
drain 5 V tolerant
Inp u t/O u tp u t
Chip config u ration/stat u s is accessed via this I2C port. This pin is tr u e open
drain, so it does not p u ll to gro u nd if power is not applied.
External reset.
Active LOW. M u st be p u lled u p to VCC33OUT. When main power is not provided
to the system, the microprocessor m u st present a high impedance of at least
100 k-ohms to RESET#. If this condition is not met, a circ u it to block the leakage
from VCC33OUT to the microprocessor GPIO may be req u ired.
69 RESET# Schmitt Inp u t
Pin
No.
Function Name Type I/O Detail of Function
I2C slave address inp u t / Transmit power sense o u tp u t.
D u ring power-on-reset (POR), this pin is u sed as an inp u t to latch the I2C
s u baddress. The level on this pin is latched when the POR transitions from the
asserted state to the de-asserted state.
70 TPWR_CI2CA LVTTL Inp u t/O u tp u t
After completion of POR, this pin is u sed as the TPWR o u tp u t. A register setting
can change this pin to show if the active port is receiving a TMDS clock.
68 INT
Schmitt Open drain
8 mA 3.3 V tolerant
O u tp u t
Interr u pt o u tp u t.
This is an open-drain o u tp u t and req u ires an external p u ll- u p resistor.
Pin
No.
Function Name Type I/O Detail of Function
Primary CEC I/O u sed for interfacing to CEC devices This signal is electrically
compliant with the CEC specification.
As an inp u t, this pin acts as an LVTTL schmitt triggered inp u t and is 5 V tolerant.
As an o u tp u t, the pin acts as an NMOS driver with resistive p u ll- u p.
This pin has an internal p u ll- u p resistor.
CEC Compliant 5V
tolerant, Schmitt
triggered, LVTTL
This signal sho u ld be connected to the CEC signal of all HDMI inp u t and o u tp u t
ports if the system s u pports j u st one CEC line.
72 CEC_A0 Inp u t/O u tp u t
OR
In a system designed to have separate CEC connectivity for the HDMI inp u t and
o u tp u t ports, this signal sho u ld be connected to the CEC signal of all the inp u t
ports s u pported in the system.
This signal and CEC_A0 each connect to a separate CEC controller within the
port processor and are independent of each other.
Secondary CEC I/O u sed for interfacing to CEC devices.
This signal is electrically compliant with the CEC specification. As an inp u t, this
pin acts as an LVTTL schmitt triggered inp u t and is 5 V tolerant. As an o u tp u t,
the pin acts as an NMOS driver with resistive p u ll- u p. This pin has an internal
p u ll- u p resistor.
CEC Compliant 5V
tolerant, Schmitt
triggered, LVTTL
This is an optional CEC signal provided for system designers who want to
implement a system with two independent CEC lines, s
u ch as a system that
s u pports a separate CEC line for the HDMI inp u t ports and the HDMI o u tp u t
ports. In the example of a DTV that provides a second HDMI o u tp u t u sing the
SiI957n port processor; this signal can be connected to the CEC signal of the
o
u tp u t port while the CEC_A1 signal is connected to the CEC signal of the inp u t
ports.
71 CEC_A1 Inp u t/O u tp u t
This signal and CEC_A1 each connect to a separate CEC controller within the
port processor and are independent of each other.
58
RX-V573/HTR-5065
RX-V573/HTR-5065