★
All voltages are measured with a 10MΩ/V DC electronic voltmeter.
★
Components having special characteristics are marked
⚠
and must be replaced
with parts having specifications equal to those originally installed.
★
Schematic diagram is subject to change without notice.
● 電圧は、内部抵抗 10MΩの電圧計で測定したものです。
● ⚠印のある部品は、安全性確保部品を示しています。部品の交換が必要な場合、
パーツリストに記載されている部品を使用してください。
● 本回路図は標準回路図です。改良のため予告なく変更することがあります。
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
1
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
T
U
V
W
A
99
DIGITAL 3/6
RX-V385/HTR-3072
A/D IN
D S P 1 _ N _ C S
M T _ D A
D S P 1 _ N _ R S T
D S P 1 _ N _ S P I R D Y
D S P 1 _ N _ I N T
D S P _ M I S O
D S P _ M O S I
D I R _ M C K
D I R _ B C K
D I R _ W C K
D I R _ S D 0
H D M I _ E A R C _ S D 3
H D M I _ E A R C _ W C K
H D M I _ E A R C _ S D 1
H D M I _ E A R C _ S D 2
H D M I _ E A R C _ D R 2
SFL_DI
E M D 1 2
EMA5
E M C K E
E M D Q M 0
T C K
E M D 1
EMA0
E M D 4
E M D Q M 1
/ E M W E
DSP1_N_INT
E M D 3
D I R _ B C K
EMBA1
/ E M W E
SFL_DO
E M C L K
EMA4
SFL_CLK
/ E M C A S
MT_DA
E M D 2
E M A 7
EMA1
D I R _ S D 0
/EMRAS
E M D Q M 0
E M D Q M 1
AUP_BCK
EMA9
DSP1_N_SPIRDY
DIR_MCK
/EMCS
EMA2
D A _ S D _ F
N _ T R S T
E M A 9
E M D 8
DA_WCK
E M B A 0
DSP_MOSI
EMA11
AUP_WCK
E M A 1 0
DSP1_N_CS
E M D 4
T M S
EMA3
E M D 9
N _ T R S T
DSP_MISO
E M A 8
E M D 5
D S P 1 _ N _ R S T
H D M I _ E A R C _ D R 2
DA_SD_CSW
H D M I _ E A R C _ S D 3
H D M I _ E A R C _ S D 1
H D M I _ E A R C _ S D 2
E M D 1 0
DA_SD_S
T D O
DA_BCK
EMA10
T D O
T C K
H D M I _ E A R C _ W C K
E M A 3
E M D 1 1
E M D 1 3
E M D 1 4
E M A 1 1
E M D 5
T D I
DSP_SCKDSP_SCK
E M D 1 1
E M D 1 2
DA_SD_F
E M D 6
E M D 1 5
E M A 0
E M D 0
/ E M C A S
E M D 7
T M S
E M D 0
E M A 6
E M D 8
E M D 1 5
E M D 3
EMA8
/ E M C S
E M B A 1
E M D 9
T D I
E M D 1 4
E M A 4
E M D 2
/ E M R A S
E M A 2
E M D 6
EMA7
E M D 1 0
E M A 5
EMBA0
E M A 1
E M D 1 3
E M D 1
EMA6
E M D 7
D S P _ S C K
A U P _ W C K
A U P _ S D 0
S R C _ W C K
A U P _ B C K
SFL_N_CSSFL_N_CS
M Z _ A D T _ S D 1
D A _ S D _ S
D A _ S D _ C S W
D I R _ W C K
D A _ B C K
D A _ W C K
D A _ A D T _ S D 0
SRC_BCK
S R C _ B C K
SRC_WCK
MZ_ADT_SD1
MZ_ADT_SD2
M Z _ A D T _ S D 2
S R C _ S D 0
DA_ADT_SD0
AUP_SD0
SRC_SD0
E M C K E
E M C L K
C 4 1 3
0 . 1 / 1 0 ( B J )
C 4 6 8
n o _ u s e
R409
100
C 4 1 0
0 . 1 / 1 0 ( B J )
D S P 1 _ N _ C S
C 4 4 5
0 . 1 / 1 0 ( B J )
C 4 1 5
0 . 1 / 1 0 ( B J )
C463
0.1/10(BJ)
D I R _ W C K
C442
no_use
D G N D
R 4 0 1
1 0 0
X L 4 1
2 0 . 0 0 0 M H Z
12
3
4
D S P _ M O S I
C 4 1 2
0 . 1 / 1 0 ( B J )
R403
1M
C457
10/10
D I R _ M C K
R425 47X4
C 4 1 8
n o _ u s e
C 4 1 1
0 . 1 / 1 0 ( B J )
C423
0.1/10(BJ)
C 4 4 7
0 . 1 / 1 0 ( B J )
C 4 4 9
0 . 1 / 1 0 ( B J )
H D M I _ E A R C _ S D 2
C 4 5 6
0 . 1 / 1 0 ( B J )
R 4 2 3
n o _ u s e
R 4 1 6
1 0 K X 4
C 4 6 7
n o _ u s e
C437
0.1/10(BJ)
C425
0.1/10(BJ)
H D M I _ E A R C _ W C K
D A _ S D _ F
M T _ D A
C422
0.1/10(BJ)
C462
no_use
D G N D
C432
0.1/10(BJ)
R414 150X4
C435
0.1/10(BJ)
C428
0.1/10(BJ)
S R C _ B C K
D S P 1 _ N _ R S T
C 4 2 7
n o _ u s e
C439
0.1/10(BJ)
H D M I _ E A R C _ D R 2
D G N D
L403
BLM21PG600SN1D
0
J 4 0 2
C 4 4 4
0 . 1 / 1 0 ( B J )
C470
0.1/10(BJ)
C 4 4 3
0 . 1 / 1 0 ( B J )
M Z _ A D T _ S D 2
C 4 5 4
0 . 1 / 1 0 ( B J )
C472
no_use
C 4 6 9
1 0 / 1 0
A U P _ B C K
C 4 4 0
n o _ u s e
C473
no_use
C 4 0 5
0 . 1 / 1 0 ( B J )
C419
0.1/10(BJ)
+ 3 . 3 D S P 1
C421
0.1/10(BJ)
R 4 2 8
4 7 X 4
R415
33X4
R420 47X4
D I R _ S D 0
C417
no_use
D G N D
C402
470P(B)
R426 47X4
C 4 1 6
0 . 1 / 1 0 ( B J )
C431
0.1/10(BJ)
R419
10K
R418
10K
C 4 5 9
n o _ u s e
D I R _ B C K
R 4 2 2
4 . 7 K X 4
C464
0.1/10(BJ)
C 4 0 1
1 0 0 0 P ( B )
R410
no_use
R434
33
C 4 5 0
0 . 1 / 1 0 ( B J )
R406 47X4
C458
10/10
R407
33
+ 3 . 3 D S P 1
C 4 6 0
0 . 1 / 1 0 ( B J )
C 4 3 6
n o _ u s e
C426
0.1/10(BJ)
D A _ S D _ S
D S P 1 _ N _ S P I R D Y
C429
0.1/10(BJ)
C 4 5 1
0 . 1 / 1 0 ( B J )
+ 1 . 2 D S P
C 4 6 6
0 . 1 / 1 0 ( B J )
C 4 0 8
0 . 1 / 1 0 ( B J )
L 4 0 1
B K P 1 0 0 5 H S 6 8 0 - T
+ 3 . 3 D S P
R 4 2 9
4 7 X 4
D A _ B C K
R413
33
C441
no_use
C 4 5 5
0 . 1 / 1 0 ( B J )
S R C _ S D 0
C433
0.1/10(BJ)
C 4 0 3
1 8 P ( C H )
C438
0.1/10(BJ)
R408
33X4
+ 1 . 2 D S P
C 4 0 4
1 8 P ( C H )
C 4 0 7
0 . 1 / 1 0 ( B J )
D A _ S D _ C S W
C424
0.1/10(BJ)
A U P _ S D 0
R 4 3 1
4 7 X 4
C 4 0 6
0 . 0 1 / 1 6 ( B )
D G N D
R424 47X4
C 4 4 8
0 . 1 / 1 0 ( B J )
C 4 3 4
n o _ u s e
H D M I _ E A R C _ S D 1
R412
33
R 4 2 1
4 . 7 K
C 4 0 9
0 . 1 / 1 0 ( B J )
H D M I _ E A R C _ S D 3
C B 4 0 1
1
2
9
8
3
4
5
6
7
D S P 1 _ N _ I N T
R 4 3 0
4 7 X 4
M Z _ A D T _ S D 1
C 4 6 5
0 . 1 / 1 0 ( B J )
D A _ W C K
L404
BKP1005HS680-T
C420
0.1/10(BJ)
C 4 4 6
0 . 1 / 1 0 ( B J )
R 4 0 2
1 0 0 K
R433
33
C 4 1 4
0 . 1 / 1 0 ( B J )
R436
22
S R C _ W C K
C461
no_use
C471
0.1/10(BJ)
D S P _ M I S O
R 4 0 5
n o _ u s e
+ 3 . 3 D S P 1
R417
33
C 4 5 2
0 . 1 / 1 0 ( B J )
C 4 5 3
0 . 1 / 1 0 ( B J )
+ 3 . 3 D S P 1
C430
0.1/10(BJ)
L 4 0 2
B K P 1 0 0 5 H S 6 8 0 - T
D S P _ S C K
A U P _ W C K
R 4 3 2
4 7 X 4
R404
4.7K
0
J 4 0 1
R411
33
L405
BLM21PG600SN1D
R435
no_use
D A _ A D T _ S D 0
R437
33
R 4 2 7
4 7
R 4 3 8
4 7
R 4 3 9
4 7
V C C
D Q 0
V C C Q
D Q 1
D Q 2
V S S Q
D Q 3
D Q 4
V C C Q
D Q 5
D Q 6
V S S Q
D Q 7
V C C
D Q M L
W E
C A S
R A S
C S
A 1 3 / B A 0
A 1 2 / B A 1
A 1 0 / A P
A 0
A 1
A 2
A 3
V C C
V S S
A 4
A 5
A 6
A 7
A 8
A 9
A 1 1
N C
C K E
C L K
D Q M U
N C
V S S
D Q 8
V C C Q
D Q 9
D Q 1 0
V S S Q
D Q 1 1
D Q 1 2
V C C Q
D Q 1 3
D Q 1 4
V S S Q
D Q 1 5
V S S
IC44
W25Q80DVSSIG
CS
DO(IO1)
WP(IO2)
GND
DI(IO0)
CLK
HOLD(IO3)/RESET
VCC
(MCU)
002.sht
001.sht
(HDMI RXTX)
AXR1[11]
D V D D
E M B _ C L K
6 4 M b i t
E M B _ D [ 1 1 ]
EMA_A[12]
D V D D
Y D 4 8 7 C 0
G P 7 [ 1 4 ]
C V D D
EMA_BA[0]
O S C O U T
EMA_OE
U S B 0 _ V D D A 1 2
T D O
A F S R 1
E M A _ D [ 3 ]
EMB_A[0]
EMB_A[6]
EMA_A[11]
C V D D
EMA_A[3]
AXR1[10]
C / S W
T M S
F L / F R
T C K
D V D D
EMA_A[2]
CVDD
A X R 1 [ 2 ]
C V D D
EMA_A[9]
SPI0_CLK
DVDD
A X R 1 [ 4 ]
GP2[5]
A X R 1 [ 1 ]
A C L K R 1
EMA_A[1]
E M B _ D [ 2 ]
C V D D
DVDD
AXR0[10]
E M B _ D [ 1 5 ]
T M S
A X R 1 [ 8 ]
AFSR0
D G N D
EMA_A[8]
C V D D
V e n d e r
AXR0[3]
AXR0[4]
A 3 V 6 4 S 4 0 G T P - 6 0
Z E N T E L
A F S X 1
EMB_A[7]
AXR0[7]
T D I
D V D D
D V D D
N _ T R S T
DVDD
E M B _ D [ 1 0 ]
EMA_A[0]
C V D D
T C K
UART0_TXD
E M B _ W E _ D Q M [ 0 ]
EMB_A[12]
E M 6 3 8 1 6 5 T S D - 6 G
R T C _ X I
AHCLKX0
AXR0[0]
D V D D
C V D D
EMA_A[7]
E M A _ D [ 6 ]
AXR0[6]
E M B _ D [ 3 ]
EMB_A[4]
T D O
SPI0_SCS[0]
S D R A M
U S B 0 _ D P
D V D D
S R L / S R R
E M B _ C A S
D V D D
AXR0[1]
R T C _ C V D D
C V D D
EMB_A[5]
R S V 2
EMB_CS[0]
N C
T R S T
AXR0[2]
U S B 0 _ D M
SPI1_CLK
E M B _ W E _ D Q M [ 1 ]
EMB_BA[0]
AHCLKR0
U S B 0 _ V D D A 3 3
CVDD
P a r t T y p e
AXR0[11]
E M B _ D [ 1 2 ]
DVDD
E M B _ D [ 0 ]
EMA_A[10]
A X R 1 [ 3 ]
CVDD
E M A _ D [ 2 ]
A H C L K X 1
T D I
EMB_A[11]
E M B _ W E
E T R O N
E M B _ D [ 4 ]
EMB_A[10]
UART0_RXD
P L L 0 _ V D D A
AXR0[9]
EMA_A[6]
SPI0_SIMO[0]
E M B _ D [ 8 ]
EMB_A[8]
DVDD
C V D D
E M B _ S D C K E
U S B 0 _ V D D A 1 8
E M A _ D [ 5 ]
Y F 5 8 7 A 0
AMUTE1
N C
SPI1_SIMO[0]
A X R 1 [ 6 ]
D V D D
SPI1_SCS[0]
EMB_A[2]
D V D D
E M B _ D [ 9 ] /
E M A _ D [ 1 ]
DVDD
EMB_A[1]
SPI0_SOMI[0]
E M B _ D [ 1 ]
EMA_BA[1]
S e r i a l F l a s h M e m o r y
CVDD
AXR1[0]
E M A _ W E
Written by YAMAHA:YJ948A0
EMA_A[5]
D V D D
P L L 0 _ V S S A
A X R 1 [ 7 ]
EMB_A[9]
UHPI_HRDY
P a r t N o .
SPI1_SOMI[0]
E S M T
AXR0[5]
DVDD
SPI1_ENA
CVDD
C V D D
E M B _ D [ 5 ]
EMB_RAS
DVDD
E M B _ D [ 1 4 ]
X 9 6 2 5 C 0
DVDD
ACLKR0
D V D D
EMB_BA[1]
E M B _ D [ 1 3 ]
EMA_D[0]
A C L K X 1
M 1 2 L 6 4 1 6 4 A - 5 T G 2 Y
EMA_A[4]
( 8 M b i t s )
P D ( + 3 . 3 V )
A X R 1 [ 5 ]
O S C I N
GP2[6]
S E R I A L F L A S H B O O T
I C 2 4 3 a l t e r n a t e t h r e e p r o d u c t s b e l o w .
ACLKX0
EMB_A[3]
O S C V S S
E M B _ D [ 6 ]
C V D D
AFSX0
E M A _ D [ 7 ]
R E S E T
E M A _ D [ 4 ]
AXR0[8]
DVDD
E M B _ D [ 7 ]
CVDD
SPI0_ENA
CVDD
005.sht
(DIR)
D m i x
S L / S R
- / L F E
004.sht
(DIR & DAC)
007.sht
(NETWORK)
B T T R A N S M I T
I C / C B / X L : 4 1 - 6 0
O T H E R : 4 0 1 - 6 0 0
D I G I T A L 3 : D S P
IC41:
D80YK113DPTP400
Digital signal processor
PLL/Clock
Generator
w/OSC
Memory Protection
C674x
TM
DSP MICRO-
PROCESSOR
Power/Sleep
Controller
Pin
Multiplexing
RTC/
32-KHz
OSC
GPIO
EDMA3
DMA
Serial Interface
External Memory Interface
Control Timers
Connectivity
Shared Memory
Audio Ports
dMAX
System Control
Peripherals
Input
Clock(s)
JTAG Interface
Switched Control Resource (SCR)
DSP Subsystem
AET
256 KB L2 RAM
32 KB
L1 Pgm
32 KB
L1 RAM
1024 KB L2 ROM
128 KB
RAM
General-
Purpose
Timer
General-
Purpose
Timer
(Watchdog)
McASP
w/FIFO
UART
I
2
C
SPI
eHRPWM
eQEP
HPI
USB2.0
OTG Ctlr
PHY
MMC/SD
(8b)
EMIFA(8b/16b)
NAND/Flash
16b SDRAM
EMIFB
SDRAM Only
(16b/32b)
eCAP
IC44
: W25Q80DVSSIG
8 M-bit flash memory with dual and quad SPI
Block Segmentation
xxFF00h
xxF000h
∙
xxFFFFh
xxF0FFh
∙
xx2F00h
xx2000h
∙
xx2FFFh
xx20FFh
∙
xx0F00h
xx0000h
∙
xx0FFFh
xx00FFh
Write Control
Logic
/WP(IO
2
)
∙
xx1F00h
xx1000h
∙
xx1FFFh
xx10FFh
∙
xxDF00h
xxD000h
Sector 15 (4KB)
Sector 14 (4KB)
Sector 13 (4KB)
Sector 2 (4KB)
Sector 1 (4KB)
Sector 0 (4KB)
∙
∙
∙
∙
xxDFFFh
xxD0FFh
∙
xxEF00h
xxE000h
∙
xxEFFFh
xxE0FFh
∙
0FFF00h
0F0000h
∙
0FFFFFh
003000h
0030FFh
002000h
0020FFh
001000h
0010FFh
0F00FFh
∙
Block 15 (64KB)
Security Register 1 - 3
∙
∙
∙
∙
∙
∙
∙
∙
∙
08FF00h
080000h
∙
08FFFFh
0800FFh
∙
Block 8 (64KB)
07FF00h
070000h
∙
07FFFFh
0700FFh
∙
Block 7 (64KB)
04FF00h
040000h
∙
04FFFFh
0400FFh
∙
Block 4 (64KB)
03FF00h
030000h
∙
03FFFFh
0300FFh
∙
Block 3 (64KB)
00FF00h
000000h
∙
00FFFFh
0000FFh
∙
Block 0 (64KB)
Write Protect Logic and Row Decode
Status
Register
High Voltage
Generators
Page Address
Latch / Counter
Byte Address
Latch / Counter
Column Decode
And 256-Byte page Buffer
Beginning
Page Address
Data
Ending
Page Address
SPI
Command
and
Control Logic
/HOLD(IO
3
)
CLK
/CS
DI(IO
0
)
DO(IO
1
)
7
6
1
5
2
3
000000h
0000FFh
SFDP Register
W25Q80DL
IC43:
EM638165TSD-6G
4M x 16 bit synchronous DRAM
CLK
CKE
CS#
RAS#
CAS#
WE#
CLOCK
BUFFER
COMMAND
DECODER
COLUMN
COUNTER
CONTROL
SIGNAL
GENERATOR
REFRESH
COUNTER
DQ Buffer
1M x 16
CELL ARRAY
(BANK #A)
Row
Decoder
1M x 16
CELL ARRAY
(BANK #B)
Row
Decoder
1M x 16
CELL ARRAY
(BANK #C)
Row
Decoder
1M x 16
CELL ARRAY
(BANK #D)
Row
Decoder
Column Decoder
Column Decoder
Column Decoder
Column Decoder
MODE
REGISTER
A11
BA0
BA1
A0–A9
DQ0–DQ15
1
54
2
53
3
52
4
51
5
50
6
49
7
48
8
47
9
46
10
45
11
44
12
43
13
42
14
41
15
40
16
39
17
38
18
37
19
36
20
35
21
34
22
33
23
32
24
31
25
30
26
29
27
28
ADDRESS
BUFFER
A10/AP
LDQM, UDQM
VSS
VDD
DQ15
DQ0
VSSQ
VDDQ
DQ14
DQ1
DQ13
DQ2
VDDQ
VSSQ
DQ12
DQ3
DQ11
DQ4
VSSQ
VDDQ
DQ10
DQ5
DQ9
DQ6
VDDQ
VSSQ
DQ8
DQ7
VSS
VDD
NC/RFU
LDQM
UDQM
WE#
CLK
CAS#
CKE
RAS#
NC
CS#
A11
BA0
A9
BA1
A8
A10/AP
A7
A0
A6
A1
A5
A2
A4
A3
VSS
VDD
Details of colored lines
Red / full line:
Power supply (+)
Red /dashed line: Power supply (-)
Orange: Signal
detect
Yellow: Clock
Green: Protection
detect
Brown: Reset
signal
Blue:
Panel key input
to DIGITAL 1/6
to DIGITAL 4/6
to DIGITAL 2/6
to DIGITAL 4/6
No replacement part available.
FLASH ROM
SDRAM
(For factory)
Summary of Contents for HTR-3072
Page 4: ...HTR 3072 K B G F L models HTR 3072 T model 4 RX V385 HTR 3072 RX V385 HTR 3072 ...
Page 6: ...RX V385 A model RX V385 B G models RX V385 F model 6 RX V385 HTR 3072 RX V385 HTR 3072 ...
Page 7: ...RX V385 L model RX V385 V P S models RX V385 J model 7 RX V385 HTR 3072 RX V385 HTR 3072 ...
Page 8: ...HTR 3072 K model HTR 3072 B G models HTR 3072 T model 8 RX V385 HTR 3072 RX V385 HTR 3072 ...
Page 9: ...HTR 3072 F model HTR 3072 L model 9 RX V385 HTR 3072 RX V385 HTR 3072 ...
Page 133: ...RX V385 HTR 3072 ...