Pin No.
Function Name (P.C.B.)
I/O
Detail of Function
1
AXR1[0]/GP4[0]
I/O
McASP1serial data
2
UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8]
I
UART0 receive data
I/O
I2C0 serial data
I
Timer0 lower input
I
BOOT[8]
3
UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9]
O
UART0 transmit data
I/O
I2C0 serial clock
I
Timer0 lower output
I
BOOT[9]
4
AXR1[10]/GP5[10]
I/O
McASP1serial data
5
DVDD
6
AXR1[11]/GP5[11]
I/O
McASP1serial data
7
SPI1_ENA/UART2_RXD/GP5[12]
I/O
SPI1enable
I
UART2 receive data
8
SPI1_SCS[0]/UART2_TXD/GP5[13]
I/O
SPI1 chip select
O
UART2 transmit data
9
SPI0_SCS[0]/ UART0_RTS /EQEP0B/GP5[4]/BOOT[4]
I/O
SPI0 chip select
O
UART0 ready-to-send output
I
eQEP0B quadrature input
I
BOOT[4]
10
CVDD
11
SPI0_CLK/EQEP1I/GP5[2]/BOOT[2]
I/O
SPI0 clock
I
eQEP1 index
I
BOOT[2]
12
SPI0_ENA/ UART0_CTS /EQEP0A/GP5[3]/BOOT[3]
I/O
SPI0 enable
I
UART0 clear-to-send input
I
eQEP0A quadrature input
I
BOOT[3]
13
SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5]
I/O
SPI1 data slave-out-master-in
I/O
I2C1 serial clock
I
BOOT[5]
14
SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6]
I/O
SPI1 data slave-in-master-out
I/O
I2C1 serial data
I
BOOT[6]
15
DVDD
16
SPI1_CLK/EQEP1S/GP5[7]/BOOT[7]
I/O
SPI1 clock
I
eQEP1 strobe
I
BOOT[7]
17
SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0]
I/O
SPI0 data slave-out-master-in
I
eQEP0 index
I
BOOT[0]
18
SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1]
I/O
SPI0 data slave-in-master-out
I
eQEP0 strobe
I
BOOT[1]
19
EMA_WAIT[0]/ UHPI_HRDY /GP2[10]
I
EMIFA wait input/interrupt
I/O
UHPI ready
20
CVDD
21
EMA_CS[3]/AMUTE2/GP2[6]
O
EMIFA Async chip select
I/O
McASP2 mute output
22
EMA_OE/UHPI_HDS1/AXR0[13]/GP2[7]
O
EMIFA output enable
I/O
UHPI data strobe
I/O
McASP0 serial data
23
EMA_CS[2]/ UHPI_HCS /GP2[5]/BOOT[15]
O
EMIFA Async chip select
I/O
UHPI chip select
I
BOOT[15]
24
DVDD
25
EMA_BA[0] / GP1[14]
O
EMIFA bank address
26
EMA_BA[1] / UHPI_HHWIL / GP1[13]
O
EMIFA bank address
I/O
UHPI half-word identification control
27
EMA_A[10] / GP1[10]
O
EMIFA address bus
28
CVDD
29
EMA_A[0] / GP1[0]
O
EMIFA address bus
30
EMA_A[1] / MMCSD_CLK / UHPI_HCNTL0 / GP1[1]
O
EMIFA address bus
O
MMCSD_CLK
I/O
UHPI access control
70
RX-V385/HTR-3072
RX-V385/HTR-3072
Summary of Contents for HTR-3072
Page 4: ...HTR 3072 K B G F L models HTR 3072 T model 4 RX V385 HTR 3072 RX V385 HTR 3072 ...
Page 6: ...RX V385 A model RX V385 B G models RX V385 F model 6 RX V385 HTR 3072 RX V385 HTR 3072 ...
Page 7: ...RX V385 L model RX V385 V P S models RX V385 J model 7 RX V385 HTR 3072 RX V385 HTR 3072 ...
Page 8: ...HTR 3072 K model HTR 3072 B G models HTR 3072 T model 8 RX V385 HTR 3072 RX V385 HTR 3072 ...
Page 9: ...HTR 3072 F model HTR 3072 L model 9 RX V385 HTR 3072 RX V385 HTR 3072 ...
Page 133: ...RX V385 HTR 3072 ...
