Yamaha DVD-S1700, Service Manual

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SDRAM DATA(11)
VDD4
VSS
SDRAM DATA(12)
SDRAM DATA(13)
SDRAM DATA(14)
SDRAM DATA(15)
VDDcore3
VSScore
SDRAM DATA(16)
SDRAM DATA(17)
SDRAM DATA(18)
SDRAM DATA(19)
SDRAM DATA(20)
SDRAM DATA(21)
SDRAM DATA(22)
SDRAM DATA(23)
SDRAM DATA(24)
SDRAM DATA(25)
VDDcore4
VSScore
SDRAM DATA(26)
SDRAM DATA(27)
SDRAM DATA(28)
SDRAM DATA(29)
SDRAM DATA(30)
SDRAM DATA(31)
VDD5
VSS
TEST IN
SDRAM ADDR(10)
SDRAM ADDR(9)
SDRAM ADDR(8)
SDRAM ADDR(7)
SDRAM ADDR(6)
VDDcore5
VSScor
SDRAM ADDR(5)
SDRAM ADDR(4)
SDRAM ADDR(3)
SDRAM ADDR(2)
SDRAM ADDR(1)
SDRAM ADDR(0)
SDRAM WEN
SDRAM RASN
SDRAM CASN
SDRAM BA1
SDRAM BA0
SDRAM CSN
SDRAM DQM
SDRAM CLKOUT
VDD6
VSS
SDRAM CLKIN
TEST3
TEST OUT0
TEST OUT1
CTLOUT0
CTLOUT1
Tristate I/O
Power
Ground
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Power
Ground
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Power
Ground
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Power
Ground
Input
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Power
Ground
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Output
Power
Ground
Input
Input
Output
Output
Tristate O/P
Tristate O/P
SDRAM data bus *
3.3 V - Power pin for IO
Ground
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
1.8 V - Power pin for core
Ground
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
1.8 V - Power pin for core
Ground
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
3.3 V - Power pin for IO
Ground
Test input - Connect to ground
SDRAM address bus *
SDRAM address bus *
SDRAM address bus *
SDRAM address bus *
SDRAM address bus *
1.8 V - Power pin for core
Ground
SDRAM address bus *
SDRAM address bus *
SDRAM address bus *
SDRAM address bus *
SDRAM address bus *
SDRAM address bus *
SDRAM write enable *
SDRAM row address select *
SDRAM column address select *
SDRAM bank select 1 *
SDRAM bank select 0 *
SDRAM CS *
SDRAM DQM *
Clock out to SDRAM *
3.3 V - Power pin for IO
Ground
Trace delayed SDRAM clock in
Test input -Connect to ground
Test output - Leave open
Test output - Leave open
Control signal output selectable as HSync1/
CSync/HRef/Monitor coast
Control signal output selectable as
Description Pin Name
No.
Internal
Pull-up/
Pull-down
Voltage
Tolerance
Drive I/O Type
5v
5v
5v
5v
5v
5v
5v
5v
5v
5v
5v
5v
5v
5v
5v
5v
5v
5v
5v
5v
5v
5v
5v
5v
5v
5v
5v
5v
5v
5v
5v
5v
5v
5v
5v
5v
5v
5v
5v
5v
5v
5v
5v
5v
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
8mA
8mA
8mA
8mA
8mA
8mA
8mA
8mA
8mA
8mA
8mA
8mA
8mA
8mA
8mA
8mA
4mA
8mA
12mA
12mA
8mA
8mA
8mA
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD