Yamaha DSP-N600, Service Manual

Page: 57 / 142

RX-N600/RX-N600D/HTR-N5060/
DSP-N600
57
RX-N600/RX-N600D/
HTR-N5060/DSP-N600
IC2 : M30625MHP-A98GP (DSP P.C.B.)
Microprocessor
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
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27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
Vref
Avcc
P97/Adtrg/Sin4
P96/ANEX1/SOUT4
P95/ANEX0/CLK4
P94/DA1/TB4in
P93/DA0/TB3in
P92/TB2in/SOUT3
P91/TB1in/SIN3
P90/TB0in/CLK3
P141
P140
BYTE
CNVss
P87/Xcin
P86/Xcout
/RESET
Xout
Vss
Xin
Vcc1
P85/NMI
P84/INT2
P83/INT1
P82/INT0
P81/TA4in/U
P80/TA4out/U
P77/TA3in
P76/TA3out
P75/TA2in/W
P74/TA2out/W
P73/CTS2/RTS2/TA1in/V
P72/CLK2/TA1out/V
P71/RXD2/SCL2/TA0in/TB5in
P70/TXD2/SDA2/TA0out
P67/TXD1/SDA1
Vcc1
P66/RXD1/SCL1
Vss
P65/CLK1
P64/CTS1/RTS1/CTS0/CLKS1
P63/TXD0/SDA0
P62/RXD0/SCL0
P61/CLK0
P60/CTS0/RTS0
P137
P136
P135
P134
P57/RDY/CLKout
P56/ALE
P55/HOLD
P54/HLDA
Vref
Avcc
CEFD
MOD0
DTFD
CKFD
LC
XMPWR
SDM
SDD
SCK
/ICCNV
NW_RST
BYTE
CNVss
MUTETI
/TIBUSY
/RES
Xout
Vss
Xin
Vcc
NMI
/INTTI
/INTDIR
/VSY
/CSDIR
/CSTI
/CSDAC
/ICDIR
/ICTI
/SPIRDY
/CEEEP
FET
DRXM
DTXM
SDA
TXDF
Vcc
SCL
RXDF
Vss
N.C.
CLKF
BSY
TXDNW
RXDNW
iPDET
iPAP
Z2RY
/4ohm
SBRY
SPC
SPB
SPA
/EMP
PRI
MCU
MCU
O
SO
SO
DA
O
SO
SI
SO
O
O
MCU
MCU
O
I
MCU
MCU
MCU
MCU
MCU
MCU
IRQ
IRQ
IRQ
O
O
O
O
O
I
O
O
SI
SO
SO
SO
MCU
SO
SO
MCU
O
SO
O
SO
SI
I
I
O
O
O
O
O
O
I
I
O
O
I
I
MCU
MCU
O
O
O
O
O
O
O
O
O
O
MCU
MCU
O
O
MCU
MCU
MCU
MCU
MCU
MCU
O
O
O
O
O
O
O
O
O
O
O
O
O
I
MCU
I
MCU
O
O
O
O
O
O
O
O
O
O
O
O
MCU
MCU
O
I
O
O
O
O
O
O
O
O
O
MCU
MCU
O
O
MCU
MCU
MCU
MCU
MCU
MCU
O
O
O
O
O
O
O
O
O
O
O
O
O
I
MCU
I
MCU
O
O
O
O
O
O
O
O
O
O
O
O
AD reference
AD power supply
FL Driver CE
MODEL distinction 0
FL Driver TxD
FL Driver CLOCK
Limiter control output
XM/DT BUS power control (U model)
Serial data output to DIR, TI (DA70Y), DAC / DIR: 4M, LSBF/TI: 1M, MSBF
Serial data input from DIR, TI (DA70Y)
Serial clock output to DIR, TI (DA70Y) DAC
Reset I2C device of CONV (RX-N600, RX-N600D, DSP-N600 models)
Reset signal to Net-module
Vss : When single chip mode is used
Vss : When single chip mode is used, Vcc : When flash writing is used
Mute of TI decoder DSP DA70Y (HI=Mute)
TI busy detection / CDDA writing data input
Reset
Oscillation output
Ground for microprocessor
Oscillation input
Power 5V for microprocessor
No used, connect Vss
Interrupt of TI decoder DSP DA70Y
Interrupt of DIR
Interrupt of vertical sync pulse (RX-N600, RX-N600D, DSP-N600 models)
Chip enable of DIR
Chip enable of TI decoder DSP DA70Y
Chip enable of DAC (2ch/8ch common)
DIR reset
Reset of TI decoder DSP DA70Y
TI DA70Y serial ready / WCK input for CDDA writing
EEPROM CE
Control of flash writing
XMDT IC RxDU (U, C models)/DAB SCL (RX-N600D model)
XMDT IC TxDU (U, C models)/DAB SDA (RX-N600D model)
IIC data I/O for VIDEO (RX-N600, RX-N600D, DSP-N600 models)
Data transmission terminal of AF220
Power 5V for microprocessor
IIC clock I/O for VIDEO, Clock speed: 100kHz
Flash ROM RxD
Ground for microprocessor
Clock transmission terminal signal output for AF220
Busy signal output for AF220
Serial data input for iPod/Net-module
Serial data input for iPod/Net-module
iPod detection
iPod accessories power detection
Impedance control /
±
B voltage control
SURROUND BACK SP relay output
CENTER and SURROUND SP relay output
FRONT B SP relay output
FRONT A SP relay output
For FLASH writing (LO)
Protection overcurrent detection
PowerOn
No. Port Name Terminal Name
I/O
Function
Pure Direct Standby Sleep