Yamaha Digital Sound Projector YSP-900, Service Manual

Page: 56 / 82

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B C D E F G H I J K L M N
YSP-900
56
★
All voltages are measured with a 10M
Ω
/V DC electronic volt meter.
★
Components having special characteristics are marked s and must be replaced
with parts having specifications equal to those originally installed.
★
Schematic diagram is subject to change without notice.
DSP 2/3
0 0
0
0
0
0
0
0
3.1
3.2
3.2
3.1
3.1
3.4
3.1
3.1
3.4
3.4
3.1
3.3
3.3
3.4
3.3
0
0
0.1
0.1
0.1
3.2
3.2
1.7
0
0
0.1
1.6
2.1
3.1
3.1
3.0
3.4
3.4
3.0
3.4
3.0
3.1
3.1
3.1
3.0
3.4
3.1
3.4
3.0
3.0
0
0
0
0
0
0.1
1.6
0
0
0
2.1
3.1
3.1
0
3.2
0.1
3.2
3.3
0
3.2
3.3
3.4
0
3.1
3.1
3.2
3.0
3.0
3.0
3.1
3.1
3.4
2.9
3.1
3.2
3.1
3.1
3.1
3.1
3.1
0
3.3
3.4
0.1
3.4
1.4
0
0
0.7
1.3
1.3
0
3.4
1.7
1.7
3.4
0
0
3.4
0
1.4
1.4
0
1.4
3.0
3.0
3.1
3.1
3.1
3.1
3.0
1.4
3.0
3.1
3.0
3.2
3.1
3.0
3.4
0
3.1
3.1
3.0
3.4
3.2
3.1
0
0
0
0
3.4
3.4
1.4
0
3.4
1.6
0
0
0
0 0 0 0
1.4
3.2
0
0
0 0
1.4
3.4
3.4
3.4
3.4
1.4 1.4
0
1.4 1.7 1.5 1.3 1.0
3.4
3.4 3.4 3.4
1.4 1.4
3.4
1.4
1.4
0
3.4
3.4
3.4
0
0
1.4
1.4
0
1.7
1.7
1.7
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
0
0
0
0
0
0
0
0
3.4
3.4
3.3
3.4
3.4
3.4
0
1.7
1.7
1.7
0.9
3.2
3.2
1.4
0
3.4
3.4 3.3 3.4
1.4 0.1 0.1 3.2 3.4
0
1.4 3.2
0
3.1 3.1 3.4
2.1 1.6 1.4
0
3.4
0
0.1 3.4
0 0 0 0 0 0 0 0 0
1.4
3.4 3.4
1.4
0 0
1.4
1.7
3.4
3.3 3.3
0 0
DSP
DRAM FLASH
DSP2
No replacement part available.
サービス部品供給なし
Pin Multiple
xing
EMIF32
L1P Cache
Direct Mapped
4K Bytes Total
Digital Signal Processors
L1D Cache
2-Way Set
Associative
4K Bytes Total
Clock Generator,
Oscillator and PLL
x4 through x25 Multipliers
/1 through /32 Dividers
Power-Down
Logic
Instruction Fetch
Instruction Dispatch
Instruction Decode
Data Path B Data Path A
B Register File
Control
Registers
C67x TM CPU
Control
Logic
In-Circuit
Emulation
Interrupt
Control
Test
A Register File
.L1t
McASP1
McASP0
McBSP1
McBSP0
I2C1
I2C0
Timer 1
Timer 0
.S1t .M1t .D1 .D2 .M2t .S2t .L2t
GP1
GP0
HPI16
Enhanced
DMA
Controller
(16 channel)
L2 Cache/
Memory
4 Banks
64K Bytes
Total
(4-Way)
L2
Memory
DA610:
192K Bytes
DA601:
64K Bytes
R2 ROM
512K
Bytes
Total
IC12 : D60YA003BPYP225
Decoder
IC14 : W9864G6EH
1M x 4 banks x 16 bits SDRAM
DQ0
DQ15
UDQM
LDQM
CLK
CKE
A10
CLOCK
BUFFER
COMMAND
DECODER
ADDRESS
BUFFER
REFRESH
COUNTER
COLUMN
COUNTER
CONTROL
SIGNAL
GENERATOR
MODE
REGISTER
CELL ARRAY
BANK #2
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #0
CELL ARRAY
BANK #3
DATA CONTROL
CIRCUIT
DQ
BUFFER
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #1
ROWDECODER
A0
A9
BS0
BS1
CS
RAS
CAS
WE
A11
ROWDECODER
COLUMN DECODER
SENSE AMPLIFIER
COLUMN DECODER
SENSE AMPLIFIER
ROWDECODER ROWDECODER
Y 4
B 2
GND 3
IC13 : SN74AHC1G08DCKR
2-input positive-AND gate
Vcc 5 A 1
A1
A15
A14
A13
A12
A11
A10
A19
A9
A8
WE#
RESET#
NC
NC
NC
RY/BY#
A17
A18
A7
A6
A5
A4
A3
A2
1
16
2
3
4
5
6
7
8
17
18
19
20
21
22
23
24
9
10
11
12
13
14
15
A16
DQ2
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
48
33
47
46
45
44
43
42
41
40
39
38
37
36
35
34
25
32
31
30
29
28
27
26
IC17 : S29AL016D70TFI020
16M-bit COMS 3.0 volt-only boot sector flash memory
Input/Output
Buffers
X- Decoder
Y-Decoder
Chip Enable
Output Enable
Logic
Erase Vo ltage
Generator
PGM Voltage
Generator
Timer
V
CC
Detector
State
Control
Command
Register
V
CC
V
SS
WE#
BYTE#
CE#
OE#
STB
STB
DQ0–DQ15 (A-1)
Sector Switches
RY/ BY#
RESET#
Data
Lat ch
Y- Gating
Cell Matrix
Ad
dr
es
s L
a
tc
h
A0–A19