Xycom XVME-976/202, Manual

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Chapter 1 – Introduction
1-17
Table 1-5. VME P2 Connector Pinouts
Name Pin Name Pin Name Pin
A1 USER I/O - 2 B1 VCC C1 USER I/O - 1
A2 USER I/O - 4 B2 GND C2 USER I/O - 3
A3 USER I/O - 6 B3 NC C3 USER I/O - 5
A4 USER I/O - 8 B4 NC C4 USER I/O - 7
A5 USER I/O - 10 B5 NC C5 USER I/O - 9
A6 USER I/O - 12 B6 NC C6 USER I/O - 11
A7 USER I/O - 14 B7 NC C7 USER I/O - 13
A8 USER I/O - 16 B8 NC C8 USER I/O - 15
A9 USER I/O - 18 B9 NC C9 USER I/O - 17
A10 USER I/O - 20 B10 NC C10 USER I/O - 19
A11 USER I/O - 22 B11 NC C11 USER I/O - 21
A12 USER I/O - 24 B12 GND C12 USER I/O - 23
A13 USER I/O - 26 B13 VCC C13 USER I/O - 25
A14 USER I/O - 28 B14 NC C14 USER I/O - 27
A15 USER I/O - 30 B15 NC C15 USER I/O - 29
A16 USER I/O - 32 B16 NC C16 USER I/O - 31
A17 USER I/O - 34 B17 NC C17 USER I/O - 33
A18 USER I/O - 36 B18 NC C18 USER I/O - 35
A19 USER I/O - 38 B19 NC C19 USER I/O - 37
A20 USER I/O - 40 B20 NC C20 USER I/O - 39
A21 USER I/O - 42 B21 NC C21 USER I/O - 41
A22 USER I/O - 44 B22 GND C22 USER I/O - 43
A23 USER I/O - 46 B23 NC C23 USER I/O - 45
A24 USER I/O - 48 B24 NC C24 USER I/O - 47
A25 USER I/O - 50 B25 NC C25 USER I/O - 49
A26 USER I/O - 52 B26 NC C26 USER I/O - 51
A27 USER I/O - 54 B27 NC C27 USER I/O - 53
A28 USER I/O - 56 B28 NC C28 USER I/O - 55
A29 USER I/O - 58 B29 NC C29 USER I/O - 57
A30 USER I/O - 60 B30 NC C30 USER I/O - 59
A31 USER I/O - 62 B31 GND C31 USER I/O - 61
A32 USER I/O - 64 B32 VCC C32 USER I/O - 63
VME-P1
Used for +5v,+12v & -12v routing only. IACKIN* tied to IACKOUT*,
BGXIN* tied to BGXOUT*.
80pin Interboard Connector 1 Pinout (P5)
This proprietary connector has all the PCI signals along with 4 separate PCI
clocks and the 4 request and grants predefined. The CPU board and the In-
terface boards will be keyed for either 3.3V or 5V signaling. The keying
mechanism is based on standoffs. At this point all CPU boards will be 5V
PCI signaling. The V/IO pins on the connector are used to define the sig-
naling level to the other PCI boards.