Xycom XVME 590, Manual

Page: 49 / 102

lXVME-500/590 Manual
February, 1988
Table 3-2. Input Mode Options
9
Mode Bits
Bit 6 Bit 5 A/D Conversion Mode
0 0 Single Channel
0 1
Sequential Channel
1 0 Random Channel
1 1 External Trigger
Single Channel Starts conversion process when reading lower 8 bits
Sequential Channel Channels are converted in a sequence, beginning
with a specific number; starts conversion process
when reading lower 8 bits
Random Channel Starts conversion after channel number is written
to Gain Channel register (in read mode; see Table
2-6)
External Trigger Starts conversion on positive trigger signal
received on Pin 50 (ground reference on Pin 49) of
of connector JKl (see Figure 3-6 for timing)
The use of input conversion modes is explained in greater detail in Section 3.4.1
D 4 This bit provides a means for a module software reset. If
“toggled” to logic ‘l’, then back to logic ‘0’, a software reset
will occur (in bits D7 and D2)
D 3
D 2
A logic ‘1’ written to this location will enable the module to
generate VMEbus interrupts (if the associated jumpers are set
appropriately; see Section 2.5.3)
This bit is an ‘interrupt-pending’ flag. Logic ‘1’ at this location
says an A/D conversion has been completed. The interrupt-pending
bit can be cleared in one of three ways:
1)
Causing a new A/D conversion (see bit D7)
2) Performing backplane or software reset (see bit D4)
3) Reading the converted input data from the lower order
data byte
Dl & D 0 : T h e s e b i t s a r e n o t u s e d b y t h e XVME-500/590 s t a t u s / c o n t r o l
register.
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