Xycom XVME-560, Manual

Page: 56 / 70

XVME-560 Manual
September, 1984
Table
B-1.
Pl - VMEbus Signal Identification
(cont’d)
Signal
Mnemonic
SYSCLK
Connector
and
Pin Number
1A: 10
Signal
Name and Description
SYSTEM CLOCK - A constant 16-MHz clock signal
that is independent of processor speed or timing.
This signal is
used for
general system timing use.
SYSFAIL* 1C: 10 SYSTEM FAIL - Open-collector driven signal that
indicates that a failure has occurred in the system.
This signal may be generated by any module on the
VMEbus.
SYSRESET* lC: 12
SYSTEM RESET - Open-collector driven signal
which, when low, will cause the system
to be reset.
WRITE* 1A: 14 WRITE - Three-state driven signal
that specifies
the data transfer cycle in
progress to be either
read or
written. A
high
level
indicates a read
operation;
a
low level indicates a write operation.
+5V STDBY 1B: 3 +5 Vdc STANDBY - This line su5 Vdc to
devices requiring battery backup.
+5V
1A: 32 +5 Vdc Power
1B: 32
-
Used by system
logic circuits.
lC: 32
2B: 1,13,32
+12v
-12v
1C: 31
1A: 31
+12 Vdc Power -
Used by
system logic circuits.
-12 Vdc Power - Used by system logic circuits.
B-4