Xycom XVME-560, Manual

Page: 51 / 70

XVME-560 Manual
September,
1984
INTERRUPT CONTROL
Interrupts for non-intelligent modules can be enabled or disabled by setting/clearing
the Interrupt Enable bit in the module status register. The status of pending on-board
interrupts can also be read from this register.
Interrupt control for intelligent
modules is handled by the Interprocessor Communications Protocol.
Communications Between Processors
Communications between an intelligent " m a s t e r " and an intelligent "slave"
I/O
module
is governed by XYCOM's Interprocessor Communication (IPC) Protocol. This protocol
involves the use of 20-byte Command Block data structures, which can be located
anywhere in shared global RAM or dual-access RAM on an
I/O module, to exchange
commands and data between a host processor and an
I/O
module.
Interprocessor
Communication Protocol is thoroughly
explained in Chapter 3 of this manual.
THE KERNEL
To standardize its XVME I/O modules, XYCOM has designed them around " k e r n e l s "
common from module to module. Each different module type consists of a standard
kernel, combined with module-dependent application circuitry. Module standardiza-
tion results in more efficient module design and allows the implementation of the
Standard I/O Architecture. The biggest benefit of standardization for intelligent
modules is that it allows the use of a common command language or protocol
(Interprocessor Communication ProtocoI
in this case).
The intelligent kernel is based around a 68000 microprocessor. This design provides
the full complement of VMEbus Requester and Interrupter options for master/slave
interfacing,
as
well
as
all of the advantages provided by the various facets of the
XYCOM Standard I/O Architecture (as covered earlier in this appendix).
The non-intelligent kernel provides the circuitry required to receive and generate all
of the signals for a
VMEbus defined
16-bit "slave" module. The non-intelligent kernel
also employs the features of the XYCOM Standard I/O Architecture (as described
earlier in this appendix).
The simplified diagrams below show
the features of both the intelligent and the non-
intelligent kernels.
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