Xycom XVME-400, Manual

Page: 49 / 83

XVME-400/40l/490/491 Manual
October, 1989
Signal
Mnemonic
IACK*
IRQl*-
IRQ7*
LWORD*
(RESERV-
ED)
SERCLK
SERDAT
SYSCLK
Table A-l. VMEbus Signal Identification (cont’d)
Connector
a n d
Pin Number
1A:20
1 B:24-30
lC:l3
2B:3
lB:21
1B:22
1A:l0
Signal Name and Description
INTERRUPT ACKNOWLEDGE: Open-collector or three-
state driven signal from any master processing an interrupt
request. It is routed via the backplane to slot 1, where it
is looped-back to become slot
1 IACKIN*
in order to start
the interrupt acknowledge daisy-chain.
INTERRUPT REQUEST
(1-7): Open-collector driven
signals, generated by an interrupter, which carry
prioritized interrupt requests. Level seven is the highest
priority.
LONGWORD: Three-state driven signal indicates that the
current transfer is a 32-bit transfer.
RESERVED: Signal line reserved for future VMEbus
enhancements. This line must not be used.
A
reserved signal which will be used as the clock for a
serial communication bus protocol which is still being
finalized,
A reserved signal which will be used as the transmission
line for serial communication bus messages.
SYSTEM CLOCK:
A
constant 16-MHz clock signal that is
independent of processor speed or timing. It is used for
general system timing use.
A-4