XVME-212 Manual
August, 1989
Register is read. This ensures that the data read from the Change and Data Registers is
from the same scan (when a Change Register read is followed by a Data Register read).
If the scanner were allowed to run, a Change Register bit could be set after the Change
register was read but before the Data Register is read. Because reading a Data Register
zeros the Change Register, any Change Register bits set between the two reads would be
lost. Stopping the scanner in this fashion ensures that no change Register bits will be lost.
3.9.3
Restarting the Scanner
If the scanner is stopped due to reading the Change Register, it can be restarted by
reading the Data Register, the Extended Status, or the Status/Control Register. The
scanner is also started up automatically after the XVME-212 is reset.
3.10
VMEbus INTERRUPTS
Each of the four Change Registers has an interrupt enable bit in the Status/Control
Register (bits 4-7). When this bit is set, a VMEbus interrupt will be generated when any
bit of the corresponding Change Register is set and the VMEbus Interrupt Enable bit (bit
3 of the Status/Control Register) is set. This alerts the CPU that an input has changed
state since the last time the CPU read the data registers.
Figure 3-5 illustrates the logic involved in generating a VMEbus interrupt. Reading the
corresponding Data Register will reset the VMEbus interrupt (because reading the Data
Registers will reset the corresponding Status/Control bit 8-11). When the VMEbus
interrupt enable (bit 3) is reset no VMEbus interrupt will be generated. By using the
interrupt mechanism, the VMEbus is relieved of the traffic required to constantly poll the
module.
The level of the VMEbus interrupt generated by the XVME-212 is determined by the
setting of Switch bank S2 (see Section 2.4.5). The IACK vector is determined by the
contents of the IACK Vector Register at location base+83H (see Section 3.6).
3-11
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