30
4.3 Advanced Chipset Features
DRAM Timing Selectable
This option refers to the method by which the DRAM timing is selected. The default is <By
SPD>.
CAS Latency Time
You can configure CAS latency time in HCLKs as 2 or 2.5 or 3. The system board designer
should set the values in this field, depending on the DRAM installed. Do not change the values
in this field unless you change specifications of the installed DRAM or the installed CPU. The
default is <Auto>.
DRMA RAS# to CAS# Delay
This option allows you to insert a delay between the RAS (Row Address Strobe) and CAS
(Column Address Strobe) signals. This delay occurs when the DRAM is written to, read from or
refreshed. Reducing the delay improves the performance of the DRAM. The default is <Auto>.
DRAM RAS# Precharge
This option sets the number of cycles required for the RAS to accumulate its charge before
the DRAM refreshes. The default setting for the Active to Precharge Delay is <3>.
Precharge dealy (tRAS)
Summary of Contents for TC-965
Page 1: ...TC 965 Embedded MiniPC User s guide ...
Page 6: ...Chapter 1 General Information ...
Page 11: ...Chapter 2 Hardware Functionality ...
Page 23: ...Chapter 3 Hardware Installation ...
Page 29: ...Chapter 4 BIOS Setup ...
Page 58: ...Appendix ...
Page 64: ...LPT Line print terminal The denomination reserved by DOS is used to denote universal parallel ...