USB Audio Design Guide
The S/PDIF transmitter core takes PCM audio samples via a channel and outputs
them in S/PDIF format to a port. A lookup table is used to encode the audio data
into the required format.
It receives samples from the Audio I/O core two at a time (for left and right). For
each sample, it performs a lookup on each byte, generating 16 bits of encoded
data which it outputs to a port.
S/PDIF sends data in frames, each containing 192 samples of the left and right
channels.
Audio samples are encapsulated into S/PDIF words (adding preamble, parity,
channel status and validity bits) and transmitted in biphase-mark encoding (BMC)
with respect to an
external
master clock.
Note that a minor change to the
SpdifTransmitPortConfig
function would enable
internal
master clock generation (e.g. when clock source is already locked to
desired audio clock).
Sample frequencies
44.1, 48, 88.2, 96, 176.4, 192 kHz
Master clock ratios
128x, 256x, 512x
Module
module_spdif_tx
Figure 17:
S/PDIF
Capabilities
3.7.1
Clocking
PORT
PORT
D-type
MCLK
XCORE Tile
S/PDIF
TX
S/PDIF
DATA
via clock block
Figure 18:
D-Type Jitter
Reduction
The S/PDIF signal is output at a rate dictated by the external master clock. The
master clock must be 1x 2x or 4x the BMC bit rate (that is 128x 256x or 512x audio
sample rate, respectively). For example, the minimum master clock frequency for
192kHz is therefore 24.576MHz.
This resamples the master clock to its clock domain (oscillator), which introduces
jitter of 2.5-5 ns on the S/PDIF signal. A typical jitter-reduction scheme is an
external D-type flip-flop clocked from the master clock (as shown in the preceding
diagram).
XM0088546.1
Summary of Contents for xCORE-200 Multi-channel Audio board
Page 6: ...1 Overview XM0088546 1...
