68
Virtex-6 FPGA Connectivity Kit Getting Started
UG664 (v1.4) July 6, 2011
Getting Started with the Virtex-6 FPGA IBERT Reference Design
d. Connect J5 to J7 (see
).
e.
Connect J11 to J12 with a
SATA loopback cable
included in the Virtex-6 FPGA
Connectivity Kit (see
).
X-Ref Target - Figure 68
Figure 68:
Configuring the SMA Transceiver Channel with External Loopback - IV
X-Ref Target - Figure 69
Figure 69:
Configuring the SMA Transceiver Channels and SATA Channels with
External Loopback - V
UG664_45_011610
UG664_46_011610
Summary of Contents for Virtex-6 FPGA
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