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Virtex-5 RocketIO GTP Transceiver User Guide

UG196 (v1.3) May 25, 2007

Appendix A:

MGT to GTP Transceiver Design Migration

R

Clocking

Virtex devices provide several available clock inputs.

shows the clocks for each

family and their respective serial speeds.

Clock selection changed slightly across the first three generations of MGTs. In contrast, the
GTP_DUAL tile significantly enhances clocking capabilities by adding dedicated clocks
routing and MUXing resources.

shows how the reference clocks are selected for

each device.

Virtex-5 FPGA

(1)

8, 12, 16, 24

Notes:

1. Because two GTP transceivers use shared PLL resources in a GTP_DUAL tile, applications where

transceivers do not have common clock settings may not be able to use both transceivers in a tile. This

will reduce the total number of available transceivers in these applications.

Table A-1:

Transceivers per Device

(Continued)

Virtex Device

# of Transceivers

Table A-2:

Available Clock Inputs

Family

Clock

Names

Differential

(Internal)

Dedicated

Routes

Max Serial

Speeds (Gb/s)

Dynamic

Switching

Package

Input Voltage

(V)

(1)

Inputs per

Device

Clocks per

Device

Virtex-II
Pro
FPGA

BREFCLK

Yes

3.125

Yes

(2)

2.5

8

(3)

2

(3)

BREFCLK2

Yes

3.125

Yes

(2)

2.5

8

(3)

2

(3)

REFCLK

2.5

Yes

(2)

2.5

8

(3)

2

(3)

REFCLK2

2.5

Yes

(2)

2.5

8

(3)

2

(3)

Virtex-4
FPGA

GREFCLK

Yes

Yes

1.0

Yes

(4)

Note 5

Note 5

REFCLK1

Yes

Yes

6.5

Yes

(4)

8

4

REFCLK2

Yes

Yes

6.5

Yes

(4)

8

4

Virtex-5
FPGA

GREFCLK

Yes

Yes

Yes

1 per

GTP_DUAL

tile

1 per

GTP_DUAL

tile

REFCLK

Yes

Yes

3.125

Yes

1 per

GTP_DUAL

tile

1 per

GTP_DUAL

tile

Notes:

1. Nominal values. Refer to the specific data sheet for the exact values.
2. Dynamic selection between the REFCLKs or the BREFCLKs. To switch from REFCLK to BREFCLK or vice versa requires

reconfiguration.

3. BREFCLK should use dedicated GCLK I/O, which decreases GCLK I/O resources for other logic (also two pins per clock).
4. Reference clock switching is done via an attribute and the DRP using the RXAPMACLKSEL, RXBPMACLKSEL, and

TXABPMACLKSEL attributes. These attributes are located at DRP address

0x5D

on bits [13:12], [11:10], and [9:8], respectively.

5. GREFCLK comes from the global clock tree and can come from any FPGA clock input. It should only be used for serial rates under

1.0 Gb/s.

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Summary of Contents for Virtex-5 RocketIO GTP

Page 1: ...R Virtex 5 RocketIO GTP Transceiver User Guide UG196 v1 3 May 25 2007...

Page 2: ...E TITLE AND NONINFRINGEMENT OF THIRD PARTY RIGHTS IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL INDIRECT EXEMPLARY SPECIAL OR INCIDENTAL DAMAGES INCLUDING ANY LOST DATA AND LOST PROFITS ARIS...

Page 3: ...d added three attributes to Table 6 8 page 105 Revised the Using the TX Phase Alignment Circuit to Bypass the TX Buffer page 106 Revised Figure 6 12 page 107 Added INTDATAWIDTH to Table 6 12 page 109...

Page 4: ...Virtex 5 RocketIO GTP Transceiver User Guide www xilinx com UG196 v1 3 May 25 2007...

Page 5: ...erview 41 Ports and Attributes 42 Description 42 Limitations 42 SmartModel Attributes 43 SIM_GTPRESET_SPEEDUP 43 SIM_PLL_PERDIV2 43 SIM_RECEIVER_DETECT_PASS 43 Power Up and Reset 43 Link Idle Reset 43...

Page 6: ...ts and Attributes 73 Description 74 GTP Reset in Response to Completion of Configuration 74 GTP Reset When the GTPRESET Port is Asserted 75 GTP Component Level Resets 75 Link Idle Reset Support 75 Res...

Page 7: ...106 Using the TX Phase Alignment Circuit to Bypass the TX Buffer 106 Using the TX Phase Alignment Circuit to Minimize TX Skew 107 TX Polarity Control 108 Overview 108 Ports and Attributes 108 Descript...

Page 8: ...136 Ports and Attributes 136 Description 137 CDR Reset 138 Tuning the CDR 139 Horizontal Sample Point Shift 140 Serial In to Parallel Out SIPO 141 Overview 141 Ports and Attributes 141 Description 14...

Page 9: ...ssing the RX Buffer while Using Built In Oversampling 167 Configurable Clock Correction 168 Overview 168 Ports and Attributes 169 Description 172 Enabling Clock Correction 172 Setting RX Buffer Limits...

Page 10: ...Board Interface Analog Design Guidelines 201 Overview 201 Ports and Attributes 201 Description 202 REFCLK Guidelines 207 Overview 207 GTP Reference Clock Checklist 209 Description 209 Oscillator Sele...

Page 11: ...31 Relative Permittivity 231 Loss Tangent 232 Skin Effect and Resistive Losses 232 Choosing the Substrate Material 232 Traces 233 Trace Geometry 233 Trace Characteristic Impedance Design 233 Trace Rou...

Page 12: ...g 261 Other Minor Differences 263 Termination 263 CRC 263 Loopback 263 Serialization 264 Defining Clock Correction and Channel Bonding Sequences 264 RXSTATUS Bus 264 Pre emphasis Differential Swing an...

Page 13: ...IO GTP Transceiver Chapter 2 RocketIO GTP Transceiver Wizard Chapter 3 Simulation Chapter 4 Implementation Chapter 5 Tile Features Chapter 6 GTP Transmitter TX Chapter 7 GTP Receiver RX Chapter 8 Cycl...

Page 14: ...ted Tri Mode Ethernet Media Access Controller available in the Virtex 5 LXT and SXT platform devices Virtex 5 Integrated Endpoint Block User Guide for PCI Express Designs This user guide describes the...

Page 15: ...c ISBN 0 7803 4703 X 7 Smith Larry D November 1984 Decoupling Capacitor Calculations for CMOS Circuits Proceedings EPEP Conference 8 Williams Ross N The Painless Guide to CRC Error Detection Algorithm...

Page 16: ...e Example Blue text Cross reference link to a location in the current document See the section Additional Documentation for details Refer to Clock Management Technology CMT in Chapter 2 for details Re...

Page 17: ...TP transceivers How to use the RocketIO GTP Wizard to configure the transceivers Mapping of transceiver instances to device resources Simulation of GTP transceiver designs Board level clocking and pow...

Page 18: ...18 www xilinx com Virtex 5 RocketIO GTP Transceiver User Guide UG196 v1 3 May 25 2007 Section 1 FPGA Level Design R...

Page 19: ...d clock correction Fixed latency modes for minimized deterministic datapath latency Out of band signaling including COM signal support for PCI Express and SATA Table 1 1 lists some of the standard pro...

Page 20: ...s The Virtex 5 Ethernet MAC User Guide provides detailed information on the Ethernet MAC The Virtex 5 Integrated Endpoint Block User Guide for PCI Express Designs provides detailed information on PCI...

Page 21: ...L X0_Y6 GTP_ DUAL X0_Y5 GTP_ DUAL X0_Y4 GTP_ DUAL X0_Y3 GTP_ DUAL X0_Y2 GTP_ DUAL X0_Y1 GTP_ DUAL X0_Y0 CMT CMT CMT CMT CMT CMT I O Column I O Column CRC Blocks CRC Blocks CRC Blocks CRC Blocks CRC Bl...

Page 22: ...TXCHARDISPMODE1 1 0 TXCHARDISPVAL1 1 0 RXPOWERDOWN0 1 0 RXSTATUS0 2 0 RXDATA0 15 0 RXNOTINTABLE0 1 0 RXDISPERR0 1 0 RXCHARISCOMMA0 1 0 RXCHARISSK0 1 0 RXRUNDISP0 1 0 RXVALID0 1 0 RXPOWERDOWN1 1 0 RXS...

Page 23: ...is guide names that end with 0 are for the GTP0 transceiver on the tile and names that end with 1 are for the GTP1 transceiver Names that do not end with 0 or 1 are shared Table 1 2 summarizes all GTP...

Page 24: ...LL page 61 Clocking page 70 Power Control page 81 DADDR 6 0 In DCLK DRP address bus Dynamic Reconfiguration Port DRP page 87 DCLK In N A DRP interface clock Dynamic Reconfiguration Port DRP page 87 DE...

Page 25: ...ect Support page 116 PLLLKDET Out Async Indicates that the VCO rate is within acceptable tolerances of the desired rate Shared PMA PLL page 61 PLLLKDETEN In Async Enables the PLL lock detector Shared...

Page 26: ...ignment and Detection page 149 RXCDRRESET0 RXCDRRESET1 In RXUSRCLK2 Reset for the RX CDR Also resets the rest of the RX PCS Reset page 73 RX Clock Data Recovery CDR page 136 RXCHANBONDSEQ0 RXCHANBONDS...

Page 27: ...d with a disparity error Configurable 8B 10B Decoder page 157 RXELECIDLE0 RXELECIDLE1 Out RXUSRCLK2 Indicates the differential voltage between RXN and RXP dropped below the minimum threshold RX OOB Be...

Page 28: ...r underflowed Oversampling page 143 RXPMASETPHASE0 RXPMASETPHASE1 In RXUSRCLK2 Aligns the PMA receiver recovered clock with the PCS user clocks allowing the RX FIFO to be bypassed Configurable RX Elas...

Page 29: ...ASS8B10B0 1 0 TXBYPASS8B10B1 1 0 In TXUSRCLK2 Controls the operation of the TX 8B 10B encoder on a per byte basis Configurable 8B 10B Encoder page 99 TXCHARDISPMODE0 1 0 TXCHARDISPMODE1 1 0 In TXUSRCL...

Page 30: ...lign their XCLKs with their TXUSRCLKs allowing their TX buffers to be bypassed and allows the XCLKs in multiple GTPs to be synchronized TX Buffering Phase Alignment and Buffer Bypass page 104 TXENPRBS...

Page 31: ...ass page 104 TXUSRCLK20 TXUSRCLK21 In N A Synchronizes the FPGA logic with the TX interface FPGA TX Interface page 91 Table 1 3 GTP_DUAL Port Summary Continued Port Dir Domain Description Section Page...

Page 32: ...D_SEQ_2_USE_1 Determines if the second channel bonding sequence is to be used Configurable Channel Bonding Lane Deskew page 177 CHAN_BOND_SEQ_LEN_0 CHAN_BOND_SEQ_LEN_1 Defines the length in bytes of t...

Page 33: ...s of clock correction sequence 1 are don t cares Configurable Clock Correction page 172 CLK_COR_SEQ_2_1_0 CLK_COR_SEQ_2_1_1 CLK_COR_SEQ_2_2_0 CLK_COR_SEQ_2_2_1 CLK_COR_SEQ_2_3_0 CLK_COR_SEQ_2_3_1 CLK_...

Page 34: ...TECT_0 MCOMMA_DETECT_1 Set to TRUE to allow minus comma detection and alignment Configurable Comma Alignment and Detection page 151 OOB_CLK_DIVIDER Sets the squelch clock rate based on CLKIN RX OOB Be...

Page 35: ...O page 111 TX OOB Beacon Signaling page 120 PMA_CDR_SCAN_0 PMA_CDR_SCAN_1 Allows direct control of the CDR sampling point RX Clock Data Recovery CDR page 137 PMA_COM_CFG Common configuration attribute...

Page 36: ...is used on the PMA side of the RX FIFO The default setting is RXREC RX recovered clock RXUSR RX USRCLK should be used when bypassing the RX buffer Configurable RX Elastic Buffer and Phase Alignment pa...

Page 37: ...erdown state in internal 25 MHz clock cycles The exact time depends on the CLKIN rate and the setting of CLK25_DIVIDER Power Control page 82 TRANS_TIME_NON_P2_0 TRANS_TIME_NON_P2_1 Transition time to...

Page 38: ...t to TXOUT TXOUTCLK when using the TX buffer Set to TXUSR TXUSRCLK when bypassing the TX buffer TX Buffering Phase Alignment and Buffer Bypass page 105 TXRX_INVERT0 TXRX_INVERT1 Controls inverters tha...

Page 39: ...the Xilinx CORE Generator tool Be sure to download the most up to date IP Update before using the Wizard Details on how to use this wizard can be found in UG188 RocketIO GTP Transceiver Wizard User G...

Page 40: ...40 www xilinx com Virtex 5 RocketIO GTP Transceiver User Guide UG196 v1 3 May 25 2007 Chapter 2 RocketIO GTP Transceiver Wizard R...

Page 41: ...lator with a SWIFT interface to support SmartModels which are encrypted versions of the HDL used for implementation of the modeled block Installed SmartModel for GTP_DUAL Correct setting of the enviro...

Page 42: ...GTP_DUAL Simulation Only Attributes Attribute Description SIM_GTPRESET_SPEEDUP This attribute shortens the time it takes to finish the GTPRESET sequence and lock the shared PMA PLL during simulation...

Page 43: ...tors do not fully model the analog PLL the GTP_DUAL Smartmodel includes an equivalent behavioral model to simulate the PLL output The SIM_PLL_PERDIV2 attribute is used by the behavioral model to gener...

Page 44: ...g src glbl v module The glbl v module connects the global signals to the design which is why it is necessary to compile this module with the other design files and load it along with the design v and...

Page 45: ...ss CLOCK ENABLE RESET begin end process COUNTER end A The VHDL code for this test bench located in EX_ROCBUF_tb vhd is listed below entity EX_ROCBUF_tb is end EX_ROCBUF_tb architecture behavior of EX_...

Page 46: ...ectory tree is XILINX virtex5 smartmodel lin image The selected options for the COMPXLIB tool are compxlib s mti_se l all arch all smartmodel_setup These options use the compxlib tool to compile all l...

Page 47: ...late PLL SPEED and SIM_PLL_PERDIV2 for the PCI Express example the following values are assigned REFCLK 100 MHz PLL_DIVSEL_REF 2 DIV 5 PLL_DIVSEL_FB 5 Using Equation 3 2 PLL SPEED is 1 25 GHz meaning...

Page 48: ...GTP Transceiver User Guide UG196 v1 3 May 25 2007 Chapter 3 Simulation R Using Equation 3 2 PLL SPEED is 1 5625 GHz meaning that the period is 640 ps Using Equation 3 3 SIM_PLL_PERDIV2 is 640 divided...

Page 49: ...k resources and to facilitate signal integrity analysis during board design The implementation flow facilitates this practice through the use of location constraints in the UCF While this chapter desc...

Page 50: ...nd contain placeholders for GTP_DUAL placement information The UCFs generated by the Wizard can then be edited to customize operating parameters and placement information for the application The secon...

Page 51: ...ST design_root gtp_dual 5 gtp_dual LOC GTP_DUAL_X0Y5 INST design_root gtp_dual 6 gtp_dual LOC GTP_DUAL_X0Y6 INST design_root gtp_dual 7 gtp_dual LOC GTP_DUAL_X0Y7 Connect the REFCLK_PAD_ N P different...

Page 52: ...t name is the name used in the UCF to map GTP_DUAL tiles instantiated in the design to specific tiles on the device The board level pin names and numbers are the names placed in the PKG file generated...

Page 53: ...5VLX50T GTP_DUAL_X0Y2 XC5VSX35T GTP_DUAL_X0Y1 XC5VSX50T GTP_DUAL_X0Y1 XC5VLX30T GTP_DUAL_X0Y0 XC5VLX50T GTP_DUAL_X0Y1 XC5VSX35T GTP_DUAL_X0Y0 XC5VSX50T GTP_DUAL_X0Y0 Right Edge of the Die AD3 AB4 AB3...

Page 54: ...X0Y7 C8 MGTREFCLKN_124 C7 MGTAVCC_124 D7 MGTAVCC_124 A6 MGTRXP1_124 A7 MGTRXN1_124 C9 MGTAVTTRX_124 A9 MGTRXP0_124 A8 MGTRXN0_124 C10 MGTAVTTTX_124 C5 MGTAVTTTX_124 B5 MGTTXP1_124 B6 MGTTXN1_124 B10 M...

Page 55: ...GTREFCLKN_114 AA3 MGTAVCC_114 AA4 MGTAVCC_114 AB1 MGTRXP1_114 AA1 MGTRXN1_114 W3 MGTAVTTRX_114 W1 MGTRXP0_114 Y1 MGTRXN0_114 AC3 MGTAVTTTX_114 V3 MGTAVTTTX_114 AC2 MGTTXP1_114 AB2 MGTTXN1_114 V2 MGTTX...

Page 56: ..._132 D4 C15 MGTAVCC_132 D5 MGTAVCC_132 A14 MGTRXP1_132 A15 MGTRXN1_132 C5 MGTAVTTRX_132 A17 MGTRXP0_132 A16 MGTRXN0_132 C1 MGTAVTTTX_132 C6 C8 C9 D9 C11 C12 C7 C14 D15 C17 C13 C18 MGTAVTTTX_132 B13 MG...

Page 57: ...2 MGTTXN0_116 Y3 MGTAVCCPLL_112 V4 MGTREFCLKP_112 XC5VLX110T GTP_DUAL_X0Y2 XC5VLX220T GTP_DUAL_X0Y2 XC5VLX330T GTP_DUAL_X0Y4 V3 MGTREFCLKN_112 W3 MGTAVCC_112 W4 MGTAVCC_112 Y1 MGTRXP1_112 W1 MGTRXN1_1...

Page 58: ...AY7 MGTAVTTTX_130 BA12 MGTTXP1_130 BA11 MGTTXN1_130 BA7 MGTTXP0_130 BA8 MGTTXN0_130 AY17 MGTAVCCPLL_134 AW15 MGTREFCLKP_134 AY15 MGTREFCLKN_134 AY16 MGTAVCC_134 AW16 MGTAVCC_134 BB17 MGTRXP1_134 BB16...

Page 59: ...the generation of a high speed serial clock resets power control and dynamic reconfiguration Correct clocking and reset behavior is critical for any GTP transceiver design This chapter describes the...

Page 60: ...OCKOUT PLLRESET PLLPOWERDOWN PLL_DIVSEL_FB 5 1 2 3 4 5 PLL_DIVSEL_REF 1 2 INTDATAWIDTH GTP0 RX Serial Clock x2 GTP0 RX Parallel Clock GTP0 TX Serial Clock GTP0 TX Parallel Clock GTP1 TX Serial Clock G...

Page 61: ...DIVSEL_FB x 4 If INTDATAWIDTH is High the feedback divider N is set to PLL_DIVSEL_FB x 5 PLL_DIVSEL_REF Controls the reference clock divider Valid settings for PLL_DIVSEL_REF are 1 and 2 PLL_RXDIVSEL_...

Page 62: ...The Virtex 5 Data Sheet specifies the operating range of the shared PLL including the marginal conditions Set the PLL clock must be within this operating range Equation 5 1 shows how to set the PLL cl...

Page 63: ...ence Clock Frequency REFCLK MHz PLL Clock Frequency GHz Reference Clock Divider Setting PLL_DIVSEL_REF Feedback Loop Divider Setting PLL_DIVSEL_FB Divider Settings PLL_RXDIVSEL_OUT_ 0 1 PLL_TXDIVSEL_O...

Page 64: ...width of 10 bits is required See Configurable 8B 10B Encoder page 98 and CPRI 2 2 4576 245 76 122 88 1 2288 1 2 1 1 2288 122 88 122 88 1 2288 1 2 2 0 6144 61 44 122 88 1 2288 1 2 4 OBSAI 2 1 536 153...

Page 65: ...ues Select the smallest divider values that result in the required PLL divider ratio In this case using PLL_DIVSEL_FB 2 and PLL_DIVSEL_REF 1 results in a ratio of two Configuring the Shared PLL for OC...

Page 66: ...mine the required line rates For Gigabit Ethernet both TX and RX use a line rate of 1 25 Gb s 2 Determine the internal datapath width Because Gigabit Ethernet uses 8B 10B encoding an internal datapath...

Page 67: ...equired 3 Determine the desired reference clock rate This example uses a reference clock running at 100 MHz 4 Calculate the required PLL clock rate Because the SIPO block uses both edges of the clock...

Page 68: ...outing Using a clock from a neighboring GTP_DUAL tile through GTP dedicated clock routing Using a clock from inside the FPGA GREFCLK Using the dedicated clock routing provides the best possible clock...

Page 69: ...P MGTREFCLKN MGTREFCLKP MGTREFCLKN GREFCLK GREFCLK GREFCLK GREFCLK GREFCLK GREFCLK GREFCLK GREFCLK Clock Muxing Clock Muxing Clock Muxing Clock Muxing Clock Muxing Clock Muxing Clock Muxing Clock Muxi...

Page 70: ...nce clock Figure 5 4 shows a differential GTP clock pin pair sourced by an external oscillator on the board Refer to Chapter 10 GTP to Board Interface REFCLK Guidelines for IBUFDS details Table 5 4 Sh...

Page 71: ...UAL tiles sourced by the external clock pin pair MGTREFCLKN MGTREFCLKP must not exceed seven 4 All the GTP_DUAL tiles between the source of the reference clock and a tile using the reference clock inc...

Page 72: ...Reset Overview The GTP_DUAL tile must be reset before any of the GTP transceivers can be used There are three ways to reset a GTP_DUAL tile 1 Power up and configure the FPGA Power up reset is covered...

Page 73: ...for the RX CDR and the RX part of the PCS for this channel This signal is driven High to cause the CDR to give up its current lock and return to the shared PLL frequency RXELECIDLERESET0 RXELECIDLERES...

Page 74: ...details about PLLPOWERDOWN The following GTP_DUAL sections are affected by the reset sequence after configuration Shared PLL GTP0 transmit section PMA and PCS GTP0 receive section PMA and PCS GTP1 tra...

Page 75: ...nt level resets All component resets are asynchronous with the exception of PRBSCNTRESET which is synchronous to RXUSRCLK2 and is effective only on its rising edge Link Idle Reset Support During opera...

Page 76: ...XRECCLK is used to generate or derive any of the USRCLKs and an Electrical Idle condition occurs the derived USRCLKs will flatline because RXRECCLK flatlines when the generating CDR is in reset In thi...

Page 77: ...by These Reset Pins Component Configuration GTPRESET PLLPOWERDOWN Falling Edge TXRESET RXCDRRESET RXRESET RXBUFRESET RXELECIDLERESET PRBSCNTRESET GTP to Board Interface Termination Resistor Calibrati...

Page 78: ...ET Table 5 8 Recommended Resets for Common Situations Situation Components to be Reset Recommended Reset 1 Power Up and Configuration Entire GTP_DUAL tile Reset after configuration is automatic Turnin...

Page 79: ...ceiver PCS in reset until the clock source is locked again If the TX or RX buffer is bypassed and phase alignment is in use phase alignment must be performed again after the clock source re locks Remo...

Page 80: ...ll the RXUSRCLK ports from the same clock source Bonding should not be attempted until the clock source is stable To provide the same recovered clock to all bonded transceivers All of the TX data sour...

Page 81: ...TX and RX can be powered down separately however for PCI Express compliance TXPOWERDOWN and RXPOWERDOWN have to be used together 00 P0 normal operation 01 P0s low recovery time powerdown 10 P1 longer...

Page 82: ...n conjunction with CLKIN determines the timing of PCIe powerdown state transitions by adjusting the internal 25 MHz clock rate PCI_EXPRESS_MODE_0 PCI_EXPRESS_MODE_1 Setting this attribute to TRUE enab...

Page 83: ...tate is indicated by the assertion of the PLLLKDET signal on the tile whose REFCLKPOWERDNB signal is asserted TX and RX Power Control When the TX and RX power control signals are used in non PCI Expre...

Page 84: ...n 00 P0 mode Transceiver TX or RX is active sending or receiving data 11 P2 mode Transceiver TX or RX is idle Table 5 13 TX and RX Power States for PCI Express Operation TXPOWERDOWN 1 0 and RXPOWERDOW...

Page 85: ...d to determine the actual rate Equation 5 6 Examples The example shown in Figure 5 10 shows the recommended method to power down an unused tile or an unused transceiver in a tile Transition time in ns...

Page 86: ...igure 5 11 4x PIPE Compatible Configuration GTP_DUAL Tile PLLPOWERDOWN REFCLKPWRDNB RXPOWERDOWN0 1 RXPOWERDOWN0 0 RXPOWERDOWN1 1 RXPOWERDOWN1 0 TXPOWERDOWN0 1 TXPOWERDOWN0 0 TXPOWERDOWN1 1 TXPOWERDOWN...

Page 87: ...he Virtex 5 Configuration Guide provides detailed information on the DRP interface Refer to Appendix D DRP Address Map of the GTP_DUAL Tile for a map of GTP_DUAL DRP attributes sorted alphabetically b...

Page 88: ...88 www xilinx com Virtex 5 RocketIO GTP Transceiver User Guide UG196 v1 3 May 25 2007 Chapter 5 Tile Features R...

Page 89: ...ta Refer to Appendix E Low Latency Design for latency information on this block diagram The key elements within the GTP transmitter are 1 FPGA TX Interface page 90 2 Configurable 8B 10B Encoder page 9...

Page 90: ...es Table 6 1 defines the FPGA TX interface ports Table 6 1 FPGA TX Interface Ports Port Dir Clock Domain Description INTDATAWIDTH In Async Specifies the width of the internal datapath for the entire G...

Page 91: ...NTDATAWIDTH 0 FTXOUTCLK Line Rate 8 INTDATAWIDTH 1 FTXOUTCLK Line Rate 10 When INTDATAWIDTH 1 the duty cycle is 60 40 instead of 50 50 TXRESET0 TXRESET1 In Async Resets the PCS of the GTP transmitter...

Page 92: ...s on the internal datapath width of the GTP_DUAL tile INTDATAWIDTH and the TX line rate of the GTP transmitter Parallel In to Serial Out PISO page 110 describes how the TX line rate is determined Equa...

Page 93: ...LKIN must have the same oscillator as their source Thus TXUSRCLK and TXUSRCLK2 must be multiplied or divided versions of CLKIN The GTP transceiver provides access to CLKIN in two ways the REFCLKOUT pi...

Page 94: ...or PLL to drive TXUSRCLK2 Figure 6 4 TXOUTCLK Drives TXUSRCLK and TXUSRCLK2 GTP Transceiver BUFG or BUFR 1 TXOUTCLK 8 or 10 Bits TXDATA TXUSRCLK TXUSRCLK2 UG196_c6_04_100406 Notes 1 Refer to the Virte...

Page 95: ...situation the frequency must be correct for all GTP transceivers and they must share the same reference clock In Figure 6 7 because the top GTP transceiver uses a two byte interface it requires a div...

Page 96: ...ate the correct USRCLK frequency In Figure 6 8 a PLL is used to generate the TXUSRCLK and TXUSRCLK2 frequencies from REFCLKOUT A DCM can be used instead of the PLL but the PLL is more convenient when...

Page 97: ...R Figure 6 8 REFCLKOUT Driving Multiple Transceivers with a 2 Byte Interface GTP Transceiver GTP_DUAL Tile GTP Transceiver UG196_c6_08_040907 PLL_BASE CLKIN RST CLKOUT0 REFCLKOUT PLLLKDET TXUSRCLK2 T...

Page 98: ...an be disabled to minimize latency Table 6 3 8B 10B Trade Offs 8B 10B Benefits 8B 10B Costs DC Balanced No increase in bit errors due to line charging on AC coupled channels Two bit overhead per byte...

Page 99: ...multiple of 10 see FPGA TX Interface page 90 for details TXCHARDISPMODE 1 corresponds to TXDATA 15 8 and TXCHARDISPMODE 0 corresponds to TXDATA 7 0 Table 6 5 page 101 shows how TXCHARDISPMODE is used...

Page 100: ...ame reason when a two byte interface is used the first byte to be transmitted byte 0 must be placed on TXDATA 7 0 and the second placed on TXDATA 15 8 This placement ensures that the byte 0 bits are a...

Page 101: ...10 bit code should be transmitted next The encoder allows the next disparity value to be controlled directly as well to accommodate protocols that use disparity to send control information For example...

Page 102: ...clock domains used in the PCS the PMA parallel clock domain XCLK and the TXUSRCLK domain To transmit data the XCLK rate must match the TXUSRCLK rate and all phase differences between the two domains...

Page 103: ...n and must always be active See Oversampling page 143 for more information about built in 5x oversampling Table 6 6 Buffering and Phase Alignment Trade Offs TX Buffer TX Phase Alignment Ease of Use Th...

Page 104: ...alf full If TXBUFSTATUS 1 becomes set it remains set until TXRESET is asserted TXENPMAPHASEALIGN In Async When activated both GTP transmitters in a GTP_DUAL tile can align their XCLKs with their TXUSR...

Page 105: ...T attributes must be set to 1 See Parallel In to Serial Out PISO page 110 PLL_TXDIVSEL_OUT_0 PLL_TXDIVSEL_OUT_1 Divides the PLL clock to produce a high speed TX clock Because both edges of the clock a...

Page 106: ...locks to stabilize then drive TXENPMAPHASEALIGN High Keep TXENPMAPHASEALIGN High unless the phase alignment procedure must be repeated Driving TXENPMAPHASEALIGN Low will cause phase alignment to be lo...

Page 107: ...be used to minimize TX skew between GTP transceivers For phase alignment to be effective TXUSRCLK for all the GTP transceivers must come from the same source and must be routed through a low skew cloc...

Page 108: ...d Attributes Table 6 10 defines the TX polarity control ports There are no attributes in this section Description The GTP transceiver can invert the polarity of its TX data before it is transmitted Th...

Page 109: ...O 150 Section 5 6 One of the recommended test patterns in the SONET specification PRBS 31 1 X28 X31 inverted 231 1 31 ITU T Recommendation O 150 Section 5 8 A recommended PRBS test pattern for 10 Giga...

Page 110: ...TST port Table 6 12 lists the available settings Parallel In to Serial Out PISO Overview The Parallel In Serial Out PISO block is the heart of the GTP TX datapath It serializes parallel data from the...

Page 111: ...t be enabled when running the GTP transceivers at line rates between 100 Mb s and 500 Mb s TRUE Built in 5x digital oversampling enabled for both GTP transceivers on the tile FALSE Digital oversamplin...

Page 112: ...urable termination impedance The impact of each of these features on signal integrity depends on the board and the receiver See Chapter 10 GTP to Board Interface for a detailed discussion of how to us...

Page 113: ...er forming a differential transmitter output pair These ports represent pads so their locations must be constrained see Chapter 4 Implementation and they must be brought to the top level of the design...

Page 114: ...gh frequencies more than low frequencies Pre emphasis is a technique used to equalize transmitted data It compensates for the excess high frequency loss by transmitting high frequency signals with mor...

Page 115: ...percentage decrease of signal amplitude for de emphasized bits at each TXPREEMPHASIS level The higher the percentage the more de emphasis is applied Be careful not to overcompensate for high frequency...

Page 116: ...erted High to indicate completion of several PHY functions including power management state transitions and receiver detection When this signal transitions during entry and exit from P2 and RXUSRCLK2...

Page 117: ...levels of TXN and TXP are compared with a threshold voltage At the end of the sequence RXSTATUS and PHYSTATUS reflect the results of the receiver detection TXDETECTRX0 TXDETECTRX1 In TXUSRCLK2 Activa...

Page 118: ...e clock and drives the RXSTATUS signals to the appropriate code After the receiver detection is completed as signaled by the assertion of PHYSTATUS TXDETECTRX must be deasserted Figure 6 17 shows this...

Page 119: ...PHY Interface for the PCI Express PIPE Specification The format of the beacon sequence is controlled by the FPGA logic Ports and Attributes Table 6 20 describes the ports that control OOB beacon sign...

Page 120: ...ence The type of COM sequence generated is controlled by the TXCOMTYPE port as shown in Table 6 20 The number of bursts in the COM sequence is controlled by the COM_BURST_VAL attribute The timing of t...

Page 121: ...to be changed at run time e g for SATA autonegotiation the GTP_DUAL Dynamic Reconfiguration port see Dynamic Reconfiguration Port DRP page 87 can be used to change the appropriate PLL_TXDIVSEL_OUT at...

Page 122: ...122 www xilinx com Virtex 5 RocketIO GTP Transceiver User Guide UG196 v1 3 May 25 2007 Chapter 6 GTP Transmitter TX R...

Page 123: ...latency information on this block diagram The key elements within the GTP receiver are 1 RX Termination and Equalization page 125 2 RX OOB Beacon Signaling page 129 3 RX Clock Data Recovery CDR page...

Page 124: ...1 3 May 25 2007 Chapter 7 GTP Receiver RX R 10 Configurable 8B 10B Decoder page 157 11 Configurable RX Elastic Buffer and Phase Alignment page 161 12 Configurable Clock Correction page 168 13 Configur...

Page 125: ...of the high pass filter are described in Table 7 1 Table 7 1 RX Termination and Equalization Ports Port Dir Clock Domain Description MGTRXN0 MGTRXN1 MGTRXP0 MGTRXP1 In Pad RX Serial Clock RXN and RXP...

Page 126: ...r AC coupling RCV_TERM_GND_0 RCV_TERM_GND_1 Activates the Ground reference for the receiver termination network TRUE Ground reference for receiver termination activated FALSE Ground reference for rece...

Page 127: ...ates the 2 3 MGTAVTTRX reference behind the built in AC coupling circuit To turn on built in AC coupling AC_CAP_DIS is set to FALSE and RCV_TERM_MID is set to TRUE To disable the built in AC coupling...

Page 128: ...7 3 Recommended RX Termination Settings Coupling Type Valid RX Termination Settings Notes DC coupled 2 3 MGTAVTTRX MGTAVTTRX The TX termination and TX termination voltage must match the selected RX t...

Page 129: ...with amplified high frequency components The ratio of the signal from the high frequency buffer and the regular wideband buffer is controlled by the RXEQMIX port Table 7 1 page 125 shows the differen...

Page 130: ...RXSTATUS1 2 0 Out RXUSRCLK2 The decoding of RXSTATUS 2 0 depends on the setting of RX_STATUS_FMT When RX_STATUS_FMT PCIE 000 Receiver not present when in receiver detection sequence Received data OK d...

Page 131: ...L_0 SATA_BURST_VAL_1 Number of bursts required to declare a COM match The default for SATA_BURST_VAL is 4 which is the burst count specified in SATA for COMINIT COMRESET and COMWAIT SATA_IDLE_VAL_0 SA...

Page 132: ...w to calculate the best value for a given squelch clock rate SATA_MIN_INIT_0 SATA_MIN_INIT_1 In SATA OOB signals are used as idles in COMINIT COMRESET and COMWAKE The minimum length of an idle that mu...

Page 133: ...MHz and as close to 25 MHz as possible In addition the MIN and MAX times for bursts and idles must be set based on the squelch clock rate The formula to set the squelch clock is shown below Equation 7...

Page 134: ...4 3 Shortest Burst width that must be accepted 101 5 1 7 6 5 1 5 1 5 1 4 341428571 Nominal Burst length 107 5 3 8 0 5 3 5 3 5 3 4 572857143 Longest Burst width that must be accepted 112 5 6 8 4 5 6 5...

Page 135: ...naling R Longest idle width that must be accepted for COMWAKE 112 5 6 8 4 5 6 5 6 5 6 4 8 MaxWakeWidth 7 11 7 7 7 6 Longest idle width that must be rejected for COMWAKE 175 8 8 13 1 8 8 8 8 8 8 7 5 Ta...

Page 136: ...RXCDRRESET0 RXCDRRESET1 In RXUSRCLK2 Individual reset signal for the RX CDR and the RX part of the PCS for this channel This signal is driven High to cause the CDR to give up its current lock and retu...

Page 137: ...ithout transitions can introduce error The RX CDR circuit can tolerate runs longer than 150 bits but designers should take steps to limit the length of runs without transitions to 150 bits or fewer Ta...

Page 138: ...lemented whenever a GTP receiver is used The RXENELECIDLERESET port enables the RXELECIDLE RESET port which is used to reset the CDR without resetting any other blocks in response to electrical idle c...

Page 139: ...nspread For SATA the interface can be asynchronous where along with instantaneous frequency differences caused by the spread spectrum modulation there can also be a 350 ppm static frequency difference...

Page 140: ...h an eye from clean data good signal integrity versus a scan of bad data This functionality is supported through the PMA_CDR_SCAN attribute Dynamic scans are performed by changing PMA_CDR_SCAN using t...

Page 141: ...must be masked to prevent an accidental change from the default value Table 7 13 SIPO Ports Port Dir Clock Domain Description INTDATAWIDTH In Async Specifies the width of the internal datapath for the...

Page 142: ...USERCLK rate of the GTP transceiver which is used internally in the PCS See Configurable RX Elastic Buffer and Phase Alignment page 161 for more details about the clock domains in the RX side of the G...

Page 143: ...ersampling Figure 7 8 GTP RX Block Diagram RX PMA RX PCS Rx EQ Rx OOB SIPO RX Polarity Over sampling UG196_c7_08_092606 Rx CDR Shared PMA PLL Divider Takes data from 10 bit datapath at 5x line rate Re...

Page 144: ...for the PMA is given by Equation 7 4 Equation 7 4 To achieve the required line rate the RX divider for the transceiver must be set so that the resulting required PLL clock rate is within the PLL opera...

Page 145: ...ip between RXUSRCLK and RXUSRCLK2 Activating and Operating the Oversampling Block After the PMA line rate and PCS datapath are set the oversampling block can be enabled by setting OVERSAMPLING_MODE to...

Page 146: ...ort is driven High to invert the polarity of incoming data Ports and Attributes Table 7 17 defines the RX polarity ports There are no attributes in this section Description The RX Polarity port is use...

Page 147: ...sing edge RXENPRBSTST0 1 0 RXENPRBSTST1 1 0 In RXUSRCLK2 Receiver test pattern checker control 00 Disable PRBS checkers 01 Enable 27 1 PRBS checker 10 Enable 223 1 PRBS checker 11 Enable 231 1 PRBS ch...

Page 148: ...sserting PRBSCNTRESET clears RXPRBSERR GTPRESET RXCDRRESET and RXRESET also reset the count Configurable Comma Alignment and Detection Overview Serial data must be aligned to symbol boundaries before...

Page 149: ...ment and Detection Ports Port Dir Clock Domain Description RXBYTEISALIGNED0 RXBYTEISALIGNED1 Out RXUSRCLK2 Signal from comma detection and realignment circuit Stays High to indicate that the parallel...

Page 150: ...latency RXENMCOMMAALIGN0 RXENMCOMMAALIGN1 In RXUSRCLK2 Aligns the byte boundary when comma minus is detected 0 Disabled 1 Enabled RXENPCOMMAALIGN0 RXENPCOMMAALIGN1 In RXUSRCLK2 Aligns the byte boundar...

Page 151: ...turns the corresponding bit in MCOMMA or PCOMMA to a don t care bit COMMA_DOUBLE_0 COMMA_DOUBLE_1 Specifies whether a comma match consists of either a comma plus or a comma minus alone or whether both...

Page 152: ...omma If COMMA_DOUBLE is TRUE the MCOMMA and PCOMMA patterns are combined so that the block searches for two commas in a row The number of bits in the comma depends on INTDATAWIDTH see Shared PMA PLL p...

Page 153: ...gnment position PCOMMA_ALIGN must be TRUE for PCOMMAs to cause RXBYTEISALIGNED to go High Similarly MCOMMA_ALIGN must be TRUE for MCOMMAs to cause RXBYTEISALIGNED to go High Commas can arrive while RX...

Page 154: ...er the data shift Figure 7 15 Comma Alignment Boundaries RXDATAWIDTH 0 1 byte 0 1 byte 1 2 byte 1 2 byte ALIGN_COMMA_WORD 1 Any Boundary 2 Even Boundary Only 1 Any Boundary UG196_c7_15_092606 2 Even B...

Page 155: ...id characters or reset 0 1 In the resync state due to a channel bonding sequence or realignment If RX_LOSS_OF_SYNC_FSM FALSE this output presents the following information about incoming data 1 1 Rece...

Page 156: ...machine can be tuned using the RX_LOS_INVALID_INCR and RX_LOS_THRESHOLD attributes RX_LOS_THRESHOLD adjusts how sensitive the LOS state machine is to bad characters by adjusting the number of charact...

Page 157: ...face only bit 0 is used RXCHARISK0 1 0 RXCHARISK1 1 0 Out RXUSRCLK2 RXCHARISK is asserted when RXDATA is an 8B 10B K character This signal is always Low when RXDEC8B10BUSE is Low RXCHARISK is a two bi...

Page 158: ...to automatically reverse the bit order of received data before decoding it Similarly because the GTP transceiver receives the right most bit first when a two byte interface is used the first byte rec...

Page 159: ...0B_VALUE or PCOMMA_10B_VALUE RX Running Disparity 8B 10B uses a running disparity system to balance the number of 1s and 0s transmitted The 8B 10B decoder tracks the running disparity of incoming data...

Page 160: ...Receiver RX R Figure 7 19 shows a waveform with a few error bytes arriving on RXDATA and the RXNOTINTABLE and RXDISPERR ports indicating the error Figure 7 19 RX Data with 8B 10B Errors RXUSRCLK2 RXDA...

Page 161: ...All RX datapaths must use one of these approaches The costs and benefits of each approach are shown in Table 7 26 Figure 7 20 Receiver Parallel Clock Domains RX Serial Clock RX PMA RX PCS RX CDR PMA P...

Page 162: ...able 7 28 RX Elastic Buffer and Phase Alignment Ports Port Dir Clock Domain Description INTDATAWIDTH In Async Specifies the width of the internal datapath for the entire GTP_DUAL tile 0 Internal datap...

Page 163: ...he GTP_DUAL tile TRUE Built in 5x oversampling enabled FALSE Built in 5x oversampling disabled TX_BUFFER_USE must be true when OVERSAMPLE_MODE is TRUE See Oversampling page 143 for the remaining confi...

Page 164: ...available Figure 7 22 shows how phase alignment allows the RX buffer to be bypassed Before phase alignment there is no guaranteed phase relationship between the parallel clock from the SIPO XCLK and...

Page 165: ...k include Finding known data in the incoming datastream for example commas or A1 A2 framing characters In general several consecutive known data patterns should be received without error to indicate a...

Page 166: ...The flow diagram in Figure 7 23 shows the series of steps required for successful RX phase alignment Any number of clock cycles can be used for the CDR lock time but using a larger number decreases t...

Page 167: ...SRCLK and the recovered clock it generates To bypass the RX buffer when OVERSAMPLING_MODE is TRUE 1 Set RX_BUFFER_USE to FALSE to bypass the RX buffer optional 2 Set RX_XCLK_SEL to RXUSR 3 Source RXUS...

Page 168: ...a stream Figure 7 25 shows a conceptual view of clock correction Clock correction should be used whenever there is a frequency difference between XCLK and RXUSRCLK It can be avoided by using the same...

Page 169: ...XCLKCORCNT1 2 0 Out RXUSRCLK2 Reports the clock correction status of the elastic buffer 000 No clock correction 001 1 sequence skipped 010 2 sequences skipped 011 3 sequences skipped 100 4 sequences s...

Page 170: ...ic buffer latency If the elastic buffer exceeds CLK_COR_MAX_LAT the clock correction circuit removes incoming clock correction sequences to prevent overflow Valid values for this attribute range from...

Page 171: ...stic buffer latency If the elastic buffer exceeds CLK_COR_MAX_LAT the clock correction circuit removes incoming clock correction sequences to prevent overflow Valid values for this attribute range fro...

Page 172: ...correction sequence This second sequence is used as an alternate sequence for clock correction when CLK_COR_SEQ_2_USE is TRUE if either sequence 1 or sequence 2 arrives clock correction is performed...

Page 173: ...te corresponds to one subsequence in clock correction sequence 1 CLK_COR_ADJ_LEN is used to set the number of subsequences to be matched If INTDATAWIDTH 1 10 bit internal datapath the clock correction...

Page 174: ...Clock Correction The clock correction circuit can be monitored using the RXCLKCORCNT and RXBUFSTATUS ports The RXCLKCORCNT entry in Table 7 30 shows how to decode the values of RXCLKCORCNT to determi...

Page 175: ...taneously on all lanes which the channel bonding circuit uses to set the latency for each lane so that data is presented without skew at the FPGA RX interface Figure 7 28 shows a conceptual view of ch...

Page 176: ...or at least one cycle when the receiver has changed the alignment between this transceiver and the master RXCHBONDI0 2 0 RXCHBONDI1 2 0 In RXUSRCLK FPGA channel bonding control Used only by slaves Dri...

Page 177: ...eed to be used CHAN_BOND_SEQ_LEN determines how much of the sequence is used for a match If CHAN_BOND_SEQ_LEN 1 only CHAN_BOND_SEQ_1_1 is used CHAN_BOND_SEQ_1_ENABLE can be used to make parts of the s...

Page 178: ...operation requires connecting the master GTP RXCHBONDO port to the RXCHBONDI port of all slaves in the group A direct connection is required for adjacent GTP transceivers To directly connect a master...

Page 179: ...VEL 3 CHAN_BOND_MODE SLAVE CHAN_BOND_LEVEL 2 CHAN_BOND_MODE SLAVE CHAN_BOND_LEVEL 1 CHAN_BOND_MODE SLAVE CHAN_BOND_LEVEL 0 UG196_c7_26_092606 Notes 1 Each box can represent either transceiver in a GTP...

Page 180: ...AN_BOND_SEQ_LEN sets the length of the sequence from one to four subsequences CHAN_BOND_SEQ_1_ sets the values of the sequence If CHAN_BOND_SEQ_2_USE is TRUE CHAN_BOND_SEQ_2_ sets the values for the a...

Page 181: ...nding and Clock Correction The clock correction see Configurable Clock Correction page 168 and channel bonding circuits both perform operations on the pointers of the RX elastic buffer Normally the tw...

Page 182: ...t width for the TX and RX paths The bit width of TX and RX must be identical for both channels 0 8 bit width 1 10 bit width 1 REFCLKOUT Out N A The REFCLKOUT port from each GTP_DUAL tile provides acce...

Page 183: ...rate which for some standards is identical to TXUSRCLK0 1 RXUSRCLK20 RXUSRCLK21 In N A Input clock used for the interface between the FPGA and the GTP transceiver For a one byte interface RXUSRCLK20 1...

Page 184: ...for RXUSRCLK depends on the internal datapath width of the GTP_DUAL tile INTDATAWIDTH and the RX line rate of the GTP receiver see Serial In to Parallel Out SIPO page 141 to see how RX line rate is d...

Page 185: ...esigner must ensure that the two are positive edge aligned If the channel is configured so the same oscillator drives the reference clock for the transmitter and the receiver REFCLKOUT or TXOUTCLK can...

Page 186: ...186 www xilinx com Virtex 5 RocketIO GTP Transceiver User Guide UG196 v1 3 May 25 2007 Chapter 7 GTP Receiver RX R...

Page 187: ...The CRC integrated blocks are independent of the transceiver blocks Figure 8 1 shows the basic port interface of the CRC block For clarification Each GTP_DUAL tile is paired with two integrated CRC b...

Page 188: ...e Clock Domain Description CRCCLK In 1 N A CRC clock CRCDATAVALIDA In 1 CRCCLK Indicates valid data on the CRCIN inputs 1 b1 Data valid 1 b0 Data invalid Deasserting this signal causes the CRC value t...

Page 189: ...clock CRCDATAVALID In 1 CRCCLK Indicates valid data on the CRCIN inputs 1 b1 Data valid 1 b0 Data invalid Deasserting this signal causes the CRC value to be held for the number of cycles that this sig...

Page 190: ...also generates a 32 bit CRC Using the CRC64 primitive consumes both CRC integrated blocks paired with a given transceiver tile For CRC64 CRCDATAWIDTH is interpreted as indicated in Table 8 5 G X X 32...

Page 191: ...NIT is a 32 bit value for the initial state of the CRC internal register Its default value is 0xFFFFFFFF The CRC_INIT value required for a given protocol is specified as part of that protocol s CRC al...

Page 192: ...s the result of the CRC calculation on the previous cycle s data and the previous cycle s CRC result In Figure 8 3 the internal CRCINTREG register shows the raw result of the CRC calculation CRCOUT pr...

Page 193: ...This usually requires some sort of decoder to find the SOF character in the incoming datastream The EOF must trigger a CRC check If fixed length frames are used this can be done with a counter If vari...

Page 194: ...es Refer to XAPP209 Ref 12 and XAPP562 Ref 13 for more information on CRC Figure 8 5 CRC Implementation CRC_CALC XOR Bank CRCOUT 31 0 Note The CRCOUT is Byte Rotated and Bit Inverted CRCINA 31 0 CRCDA...

Page 195: ...e transceiver at the far end of the link Loopback testing can be used either during development or in deployed equipment for fault isolation The traffic patterns used can be either application traffic...

Page 196: ...ved The test data is looped back before passing the parallel to serial and the serial to parallel converter All analog high speed circuits in the PMA section can be completely powered down Figure 9 2...

Page 197: ...Conditions and Limitations In the near end PMA loopback mode the TXDATA input is routed through the PMA serialized and then looped back in through the RX side of the PMA and back out to RXDATA When th...

Page 198: ...he complete PMA section including the serial to parallel and parallel to serial conversion Almost the entire PCS section is bypassed because the RX serial inputs are looped back to the TX serial outpu...

Page 199: ...n the PCS section and the received data is presented to the user logic The transmit data of the user logic is not transmitted when this mode is activated This mode is a PCI Express compliant loopback...

Page 200: ...200 www xilinx com Virtex 5 RocketIO GTP Transceiver User Guide UG196 v1 3 May 25 2007 Chapter 9 Loopback R...

Page 201: ...and the Printed Circuit Board Ref 6 by Mark I Montrose and sponsored by the IEEE Electromagnetic Compatibility Society for additional guidelines Implementation of these guidelines not only improves s...

Page 202: ...evice requires a filter circuit on the MGTAVTTRXC pin which powers the resistor calibration circuit of the device MGTAVTTTX In MGTAVTTTX is the analog supply for the transmitter termination and driver...

Page 203: ...r the exact values based on operating conditions especially voltage and temperature Figure 10 1 Resistor Calibration Circuit MGTAVTTTX RREF External 50 Precision 1 Resistor MGTRREF Package Pin Interna...

Page 204: ...1 2V AVCC_PLL 1 0 22 F 10V X7R FERRITE 220 220 100 MHz 0 22 F 10V X7R FERRITE 220 220 100 MHz 0 22 F 10V X7R FERRITE 220 220 100 MHz 0 22 F 10V X7R UG196_c10_03_041907 Notes 1 These analog supplies M...

Page 205: ...an be overwritten independently for each transceiver by using the TERMINATION_CTRL and TERMINATION_OVRD attributes This feature is intended for experimental purposes only Figure 10 5 Calibration Resul...

Page 206: ...e 0 0 0 0 0 103 0 128 8 77 3 0 0 0 0 1 97 8 122 3 73 4 0 0 0 1 0 93 2 116 4 69 9 0 0 0 1 1 88 9 111 1 66 7 0 0 1 0 0 85 0 106 3 63 8 0 0 1 0 1 81 5 101 9 61 1 0 0 1 1 0 78 2 97 8 58 7 0 0 1 1 1 75 2 9...

Page 207: ...for a GTP transceiver design Figure 10 6 illustrates the convention for the single ended clock input voltage swing peak to peak as used in the GTP transceiver portion of the Virtex 5 Data Sheet Figure...

Page 208: ...mode voltage of this differential reference clock input pair is 2 3 of MGTAVCCPLL If the common mode voltage of the driving clock source is different from the common mode voltage of the differential...

Page 209: ...ibution system requires a careful selection of components as well as a proper board layout to ensure that overall system requirements are met When designing a clocking system for a design with a GTP t...

Page 210: ...ut is used In this configuration the GTP_DUAL primitive that sources the clock is located in the middle of seven GTP_DUAL primitives that are direct neighbors to each other If a clock multiplexer with...

Page 211: ...ors free simulation tools Maxim http www maxim ic com Voltage regulators Micrel http www micrel com Oscillators clock buffers SY100EP14U 1 5 driver with 2 1 MUX Murata http www murata com EMI suppress...

Page 212: ...RR over frequency are often neglected but are very important selection criteria As a rule of thumb guideline any substantial noise in the frequency range of 1 MHz and above on the power supply lines c...

Page 213: ...he PSRR of the regulator in this example has a local minimum of rejection around 300 kHz extra care must be taken if the sourcing power supply has spurs or high amplitude noise in this frequency range...

Page 214: ...especially when it comes to high temperature Place if possible the regulator close to the filter network Place the filter network as close as possible to the analog supply pin that it sources Remember...

Page 215: ...twork as close as possible to the device power pin Ensure a low inductance connection between the capacitor and the power pin Simulate the filter circuit and optimize it if possible Isolate the analog...

Page 216: ...uits For an in depth discussion on via crosstalk and calculations of mutual inductance for various via configurations refer to High Speed Signal Propagation Advanced Black Magic by Howard Johnson and...

Page 217: ...Escape Example page 252 for information on escaping of SelectIO adjacent to GTP transceiver analog supply pins The SelectIO signals that have the largest impact on GTP transceiver performance are tho...

Page 218: ...5 MGT116 J5 H5 L4 MGT112 P5 MGT114 AA5 AB5 AC4 MGT118 AG5 AF5 AH5 MGT122 AK6 AH5 AJ6 MGT126 1 AK8 AK7 AK9 AM10 Notes 1 GTP_DUAL only available on XC5LX110T devices Table 10 9 SelectIO Adjacent to MGTC...

Page 219: ...AG4 MGT118 AL5 AK5 AN4 MGT122 AT5 AV5 MGT126 AV5 AV6 MGT130 1 AV10 AV9 AV11 AW12 MGT134 1 AV16 AV15 AW18 Notes 1 GTP_DUAL only available on XC5LX330T devices Table 10 11 SelectIO Adjacent to MGTCLK F...

Page 220: ...220 www xilinx com Virtex 5 RocketIO GTP Transceiver User Guide UG196 v1 3 May 25 2007 Chapter 10 GTP to Board Interface R...

Page 221: ...gns with high speed transceivers These guidelines have been used to create boards that have successfully operated at serial transmission rates in excess of 10 Gb s Although designing for 10 Gb s opera...

Page 222: ...222 www xilinx com Virtex 5 RocketIO GTP Transceiver User Guide UG196 v1 3 May 25 2007 Section 2 Board Level Design R...

Page 223: ...ile a more comprehensive list of transitions is discussed in Chapter 13 Design of Transitions some common transitions are Ball grid array BGA to PCB microstrip Microstrip to stripline vias DC blocking...

Page 224: ...lied to transceiver power supply designs Linear regulators are required for directly sourcing the power supplies Although switching regulators are an attractive option in applications requiring high p...

Page 225: ...ck Clock Sources A high quality crystal oscillator is essential for good performance The oscillator manufacturer s power supply design guide must be followed When choosing alternate clock sources the...

Page 226: ...ates the common modes of the two devices and is the preferred configuration in hot plug applications The capacitor prevents any DC current from flowing between connected devices Some transceivers have...

Page 227: ...e for an extended period of time When this happens charge accumulates on the blocking capacitors and a DC offset is added or subtracted from V2 This offset results in what is known as baseline wander...

Page 228: ...pacitor R 2 x RTERM t is the total discharge time which is equal to NCIDT The slope is defined by Equation 11 3 Equation 11 3 Substituting Equation 11 2 and Equation 11 3 into Equation 11 1 and solvin...

Page 229: ...s for this case more extensive analysis beyond the scope of this document is required SelectIO to Serial Transceiver Crosstalk Guidelines The breakout of SelectIO signals adjacent to transceiver analo...

Page 230: ...se SelectIO nets in the highest available routing layer Do not use SelectIO blocks adjacent to REFCLK pins because the REFCLK pins are a reference clock source to the transceivers either in the same t...

Page 231: ...tend to the frequency in Equation 12 1 For example a 10 Gb s signal with a 10 ps rise time has a bandwidth from 10 GHz to 35 GHz Dielectric Losses The amount of signal energy lost into the dielectric...

Page 232: ...itude of the higher harmonics with the highest frequency harmonics being most affected In the case of 10 Gb s signals even the fundamental frequency can be attenuated to some degree when using FR4 For...

Page 233: ...e of thumb tight coupling within a differential pair is achieved by spacing them no more than four trace widths apart Wider traces create a larger cross sectional area for current to flow and reduce r...

Page 234: ...good PCB manufacturer understands controlled impedance and allows fine adjustments for line widths to produce a Z0O of 50 The PCB manufacturer also provides the parameters necessary for the specific...

Page 235: ...ed Mitered 45 degree bends are to be used instead At a 90 degree bend the effective width of the trace changes causes an impedance discontinuity due to the capacitive coupling of the additional conduc...

Page 236: ...r and dielectric along the length of the cable The highest quality cable shows little variation in these dimensions and also has a wide bandwidth with low loss at high frequencies Connectors The conne...

Page 237: ...quency response identical to that of a lumped capacitor over a wide frequency band By design adding inductance cancels this excess capacitance in many cases except when impacted by density concerns an...

Page 238: ...se The respective equations for capacitance and inductance are Equation 13 1 Equation 13 2 Figure 13 3 shows the integration of the normalized TDR area Figure 13 1 TDR Signature of Shunt Capacitance F...

Page 239: ...citance to a nearby reference plane In the following example a 5 mil trace with a Z0 of 50 transitions to an 0402 SMT pad that is 28 mils wide all over 3 mils of FR4 Using a 2D field solver on these d...

Page 240: ...ield solver is then used to verify this result to a greater degree of accuracy Figure 13 6 shows the ground plane cleared away exactly as it was for the 2D simulation Using frequency domain analysis w...

Page 241: ...MT pad without the ground plane cleared from underneath The blue curve shows that clearing out the ground plane removes much of the excess capacitance This improvement can be quantified using Equation...

Page 242: ...d transition Excess capacitance is reduced by 15x and return loss is improved by 20 dB Figure 13 9 TDR Results Comparing 0402 Pad Structures Figure 13 10 TDR Results Comparing 0402 Pad Structures 0 10...

Page 243: ...ferential via Ground vias are connected to each ground plane in the stackup while signal layers only contain pads for the entry and exit layers Figure 13 11 840 fF Excess Capacitance with Ground Plane...

Page 244: ...raints or the lack thereof the dimensions can be scaled accordingly to preserve the ratios of each dimension relative to the others Such scaling preserves the impedance performance of the differential...

Page 245: ...of excess capacitance Because excess capacitance is a single pole response simple extrapolation rules can be used For example a shift to 34 dB return loss doubles the excess capacitance Due to the exc...

Page 246: ...ellent performance and because of the points listed in the previous paragraph Backplane Connectors There are numerous signal integrity issues associated with backplane connectors including P N signal...

Page 247: ...b s Figure 13 17 through Figure 13 19 show that phase mismatch is reduced to 0 75 with jog outs and 0 3 with jog outs and plane cutouts The combination of jog outs and plane cutouts yields simulation...

Page 248: ...e helpful as shown in Figure 13 20 Figure 13 18 Simulated Return Loss of 45 Degree Bends with Jog Outs Figure 13 19 Simulated Phase Response of 45 Degree Bends with Jog Outs 10 20 30 40 50 60 1E8 1E9...

Page 249: ...UG196 v1 3 May 25 2007 Microstrip Stripline Bends R Figure 13 20 Measured TDR of 45 Degree Bends with and without Jog Outs UG196_c13_20_051406 No Jog outs No Jog outs With Jog outs With Jog outs Turn...

Page 250: ...250 www xilinx com Virtex 5 RocketIO GTP Transceiver User Guide UG196 v1 3 May 25 2007 Chapter 13 Design of Transitions R...

Page 251: ...eventually have to be spread out to match connector pin spacings For transitions large clearances of planes must be provided around and below transitions to limit excess capacitance Transitions are s...

Page 252: ...rip is used to escape When there is adequate spacing from the BGA the optimized GSSG differential vias are used to change layers if needed It is recommended that these vias be staggered as shown in Fi...

Page 253: ...hs as shown in Figure 14 3 that require PCB trace lengths to be adjusted to compensate for the skew Figure 14 4 shows an example design where the traces are preskewed to compensate for P N length mism...

Page 254: ...Figure 14 4 the antipad size is maximized such that the ground reference for the traces extends beyond the edge of the striplines by about 3 mils All power and ground planes that do not provide an imp...

Page 255: ...nsceiver User Guide www xilinx com 255 UG196 v1 3 May 25 2007 R Section 3 Appendices MGT to GTP Transceiver Design Migration OOB Beacon Signaling 8B 10B Valid Characters DRP Address Map of the GTP_DUA...

Page 256: ...256 www xilinx com Virtex 5 RocketIO GTP Transceiver User Guide UG196 v1 3 May 25 2007 Section 3 Appendices R...

Page 257: ...ary Differences Virtex 5 LXT and SXT FPGAs are a different family from the Virtex II Pro and Virtex 4 families The Virtex 5 LXT and SXT devices are not pin compatible with these previous generation de...

Page 258: ...ternal Dedicated Routes Max Serial Speeds Gb s Dynamic Switching Package Input Voltage V 1 Inputs per Device Clocks per Device Virtex II Pro FPGA BREFCLK Yes 3 125 Yes 2 2 5 8 3 2 3 BREFCLK2 Yes 3 125...

Page 259: ...PCS and PMA REFCLK REFCLK2 BREFCLK BREFCLK2 REF_CLK_V_SEL Virtex II Pro FPGA 0 1 PMA CLKSEL REFCLK_OUT to PCS and PMA REFCLK1 REFCLK2 Virtex 4 FPGA GREFCLK Note All Virtex 4 clocks are differential UG...

Page 260: ...ne multiply ratio is used for both in Virtex 5 devices Others Yes 2 Yes 2 Yes 2 Notes 1 Encoding and clocks must be done in the FPGA logic 2 Depending on encode some functionality must be done in the...

Page 261: ...2 Because the two transceivers that share a tile have common power pins the number of power supply filtering components is reduced Table A 7 shows the power pin voltages for all Virtex families and Fi...

Page 262: ...5V 2 5V VTTXA VTTXB VTRXA VTRXB Notes Notes 1 Nominal values Refer to the device data sheets for values and operating conditions 1 Capacitors are 0402 0 22 F 2 Ferrite beads are MP21608S221A 3 MGTVRE...

Page 263: ...the Virtex transceivers have evolved to improve flexibility Virtex II Pro MGTs have two loopback modes and Virtex 4 MGTs have four loopback modes Table A 10 shows this evolution Table A 8 Termination...

Page 264: ...Virtex 5 GTP transceivers Table A 11 CLK_COR_SEQ and CHAN_BOND_SEQ Sequences Bit Definition Virtex II Pro MGT Virtex 4 MGT Virtex 5 GTP Transceiver 8B 10B encoded definition 00110111100 1 00110111100...

Page 265: ...TXSLEWRATE TXPOST_PRDRV_DAC TXDAT_PRDRV_DAC TXPOST_TAP_PD TXPREEMPHASIS 2 0 Controls differential amplitude of the transmitted signal TX_DIFF_CTRL TXPRE_TAP_DAC TXPOST_TAP_DAC TXDAT_TAP_DAC TX_DIFF_BO...

Page 266: ...266 www xilinx com Virtex 5 RocketIO GTP Transceiver User Guide UG196 v1 3 May 25 2007 Appendix A MGT to GTP Transceiver Design Migration R...

Page 267: ...tage drops below a preset threshold level the receiver detects the signal as an OOB signal Figure B 1 illustrates this concept TX OOB Beacon Signaling page 119 and RX OOB Beacon Signaling page 129 pro...

Page 268: ...from powerdown states A beacon is the transmission of K28 5 COM characters A beacon sequence can have a frequency anywhere from 30 kHz to 500 MHz The PCI Express specification describes the beacon me...

Page 269: ...00111 0100 011000 1011 D1 0 000 00001 011101 0100 100010 1011 D2 0 000 00010 101101 0100 010010 1011 D3 0 000 00011 110001 1011 110001 0100 D4 0 000 00100 110101 0100 001010 1011 D5 0 000 00101 101001...

Page 270: ...101101 1001 010010 1001 D3 1 001 00011 110001 1001 110001 1001 D4 1 001 00100 110101 1001 001010 1001 D5 1 001 00101 101001 1001 101001 1001 D6 1 001 00110 011001 1001 011001 1001 D7 1 001 00111 1110...

Page 271: ...10 0101 D3 2 010 00011 110001 0101 110001 0101 D4 2 010 00100 110101 0101 001010 0101 D5 2 010 00101 101001 0101 101001 0101 D6 2 010 00110 011001 0101 011001 0101 D7 2 010 00111 111000 0101 000111 01...

Page 272: ...101101 0011 010010 1100 D3 3 011 00011 110001 1100 110001 0011 D4 3 011 00100 110101 0011 001010 1100 D5 3 011 00101 101001 1100 101001 0011 D6 3 011 00110 011001 1100 011001 0011 D7 3 011 00111 1110...

Page 273: ...10 1101 D3 4 100 00011 110001 1101 110001 0010 D4 4 100 00100 110101 0010 001010 1101 D5 4 100 00101 101001 1101 101001 0010 D6 4 100 00110 011001 1101 011001 0010 D7 4 100 00111 111000 1101 000111 00...

Page 274: ...101101 1010 010010 1010 D3 5 101 00011 110001 1010 110001 1010 D4 5 101 00100 110101 1010 001010 1010 D5 5 101 00101 101001 1010 101001 1010 D6 5 101 00110 011001 1010 011001 1010 D7 5 101 00111 1110...

Page 275: ...10 0110 D3 6 110 00011 110001 0110 110001 0110 D4 6 110 00100 110101 0110 001010 0110 D5 6 110 00101 101001 0110 101001 0110 D6 6 110 00110 011001 0110 011001 0110 D7 6 110 00111 111000 0110 000111 01...

Page 276: ...101101 0001 010010 1110 D3 7 111 00011 110001 1110 110001 0001 D4 7 111 00100 110101 0001 001010 1110 D5 7 111 00101 101001 1110 101001 0001 D6 7 111 00110 011001 1110 011001 0001 D7 7 111 00111 1110...

Page 277: ...trol K Characters Special Code Name Bits HGF EDCBA Current RD abcdei fghj Current RD abcdei fghj K28 0 000 11100 001111 0100 110000 1011 K28 1 001 11100 001111 1001 110000 0110 K28 2 010 11100 001111...

Page 278: ...278 www xilinx com Virtex 5 RocketIO GTP Transceiver User Guide UG196 v1 3 May 25 2007 Appendix C 8B 10B Valid Characters R...

Page 279: ...inary values The mappings for these values are shown in Table D 1 For attributes not listed in Table D 1 use the following rules to determine the binary mapping Attributes with TRUE FALSE values use 1...

Page 280: ...0 6 101 10 110 12 111 PLL_DIVSEL_FB 1 10000 2 00000 3 00001 4 00010 5 00110 PLL_DIVSEL_REF 1 010000 2 000000 PLL_RXDIVSEL_OUT 1 00 2 01 4 10 PLL_TXDIVSEL_COMM_OUT 1 00 2 01 4 10 PLL_TXDIVSEL_OUT 1 00...

Page 281: ...ble D 2 lists the DRP addresses according to attribute name RX_LOS_THRESHOLD 4 000 8 001 16 010 32 011 64 100 128 101 256 110 512 111 RX_SLIDE_MODE PCS 0 PMA 1 RX_STATUS_FMT PCIE 0 SATA 1 RX_XCLK_SEL...

Page 282: ...0 31 AC_CAP_DIS_0 49 14 AC_CAP_DIS_1 6 1 ALIGN_COMMA_WORD_0 2b 12 ALIGN_COMMA_WORD_1 24 3 CHAN_BOND_1_MAX_SKEW_0 2c 0 2b 15 2b 14 2b 13 CHAN_BOND_1_MAX_SKEW_1 23 15 24 0 24 1 24 2 CHAN_BOND_2_MAX_SKEW...

Page 283: ...1 11 21 12 21 13 21 14 21 15 22 0 22 1 CHAN_BOND_SEQ_1_4_0 2f 1 2f 0 2e 15 2e 14 2e 13 2e 12 2e 11 2e 10 2e 9 2e 8 CHAN_BOND_SEQ_1_4_1 20 14 20 15 21 0 21 1 21 2 21 3 21 4 21 5 21 6 21 7 CHAN_BOND_SEQ...

Page 284: ...AN_BOND_SEQ_2_4_0 48 3 48 2 48 1 48 0 47 15 47 14 47 13 47 12 47 11 47 10 CHAN_BOND_SEQ_2_4_1 7 12 7 13 7 14 7 15 8 0 8 1 8 2 8 3 8 4 8 5 CHAN_BOND_SEQ_2_ENABLE_0 39 14 39 15 3a 0 3a 1 CHAN_BOND_SEQ_2...

Page 285: ..._KEEP_IDLE_1 16 10 CLK_COR_MAX_LAT_0 38 15 39 0 39 1 39 2 39 3 39 4 CLK_COR_MAX_LAT_1 17 0 16 15 16 14 16 13 16 12 16 11 CLK_COR_MIN_LAT_0 38 9 38 10 38 11 38 12 38 13 38 14 CLK_COR_MIN_LAT_1 17 6 17...

Page 286: ...15 18 14 18 13 18 12 18 11 18 10 18 9 18 8 CLK_COR_SEQ_1_3_0 36 4 36 5 36 6 36 7 36 8 36 9 36 10 36 11 36 12 36 13 CLK_COR_SEQ_1_3_1 19 11 19 10 19 9 19 8 19 7 19 6 19 5 19 4 19 3 19 2 CLK_COR_SEQ_1_4...

Page 287: ...33 11 33 12 33 13 33 14 33 15 34 0 34 1 CLK_COR_SEQ_2_3_1 1c 7 1c 6 1c 5 1c 4 1c 3 1c 2 1c 1 1c 0 1b 15 1b 14 CLK_COR_SEQ_2_4_0 32 14 32 15 33 0 33 1 33 2 33 3 33 4 33 5 33 6 33 7 CLK_COR_SEQ_2_4_1 1...

Page 288: ..._VAL_0 32 5 32 6 32 7 32 8 COM_BURST_VAL_1 1d 10 1d 9 1d 8 1d 7 COMMA_10B_ENABLE_0 31 11 31 12 31 13 31 14 31 15 32 0 32 1 32 2 32 3 32 4 COMMA_10B_ENABLE_1 1e 4 1e 3 1e 2 1e 1 1e 0 1d 15 1d 14 1d 13...

Page 289: ...31 0 31 1 31 2 31 3 31 4 31 5 31 6 MCOMMA_10B_VALUE_1 1f 2 1f 1 1f 0 1e 15 1e 14 1e 13 1e 12 1e 11 1e 10 1e 9 MCOMMA_DETECT_0 30 12 OOB_CLK_DIVIDER 26 14 26 13 26 12 OOBDETECT_THRESHOLD_0 3a 3 3a 4 3a...

Page 290: ...8 2 28 1 28 0 27 15 27 14 27 13 27 12 27 11 27 10 27 9 27 8 27 7 27 6 27 5 27 4 27 3 27 2 27 1 27 0 PCOMMA_DETECT_1 9 11 PLL_DIVSEL_FB 29 0 28 15 28 14 28 13 28 12 PLL_DIVSEL_REF 4 9 4 10 4 11 4 12 4...

Page 291: ...1 6 5 6 4 7 5 7 4 7 3 7 2 7 11 7 10 7 9 7 8 7 7 6 6 6 2 7 0 6 15 6 14 6 13 6 12 6 11 6 10 6 9 6 8 6 7 7 6 6 3 PRBS_ERR_THRESHOLD_0 42 4 42 5 42 6 42 7 42 8 42 9 42 10 42 11 42 12 42 13 42 14 42 15 43...

Page 292: ...TCH_1 0d 13 RX_LOS_INVALID_INCR_0 41 15 42 0 42 1 RX_LOS_INVALID_INCR_1 0e 0 0d 15 0d 14 RX_LOS_THRESHOLD_0 41 11 41 12 41 13 RX_LOS_THRESHOLD_1 0e 4 0e 3 0e 2 RX_LOSS_OF_SYNC_FSM_0 41 14 RX_LOSS_OF_S...

Page 293: ...ATA_IDLE_VAL_1 0e 13 0e 12 0e 11 SATA_MAX_BURST_0 40 12 40 13 40 14 40 15 41 0 41 1 SATA_MAX_BURST_1 0f 3 0f 2 0f 1 0f 0 0e 15 0e 14 SATA_MAX_INIT_0 40 6 40 7 40 8 40 9 40 10 40 11 SATA_MAX_INIT_1 0f...

Page 294: ...MINATION_CTRL 29 5 29 4 29 3 29 2 29 1 TERMINATION_OVRD 29 6 TRANS_TIME_FROM_P2_0 3d 13 3d 14 3d 15 3e 0 3e 1 3e 2 3e 3 3e 4 3e 5 3e 6 3e 7 3e 8 3e 9 3e 10 3e 11 3e 12 TRANS_TIME_FROM_P2_1 12 2 12 1 1...

Page 295: ...3c 11 3c 12 TRANS_TIME_TO_P2_1 14 2 14 1 14 0 13 15 13 14 13 13 13 12 13 11 13 10 13 9 13 8 13 7 13 6 13 5 13 4 13 3 TX_BUFFER_USE_0 3b 12 TX_BUFFER_USE_1 14 3 TX_DIFF_BOOST_0 4a 13 TX_DIFF_BOOST_1 5...

Page 296: ...DRP address and bit location Table D 3 DRP Addresses 00 through 07 Table D 4 DRP Addresses 08 through 0F Table D 5 DRP Addresses 10 through 17 Table D 6 DRP Addresses 18 through 1F Table D 7 DRP Addre...

Page 297: ...o Not Modify PMA_RX_ CFG_1 11 PMA_RX_ CFG_1 23 7 Do Not Modify Do Not Modify Do Not Modify Do Not Modify CLKSOUTH_ SEL Do Not Modify PMA_RX_ CFG_1 22 PMA_RX_ CFG_1 10 8 Do Not Modify Do Not Modify Do...

Page 298: ...THRESHOLD _1 5 RX_STATUS_ FMT_1 SATA_MAX_ INIT_1 3 7 CHAN_ BOND_ SEQ_2_3_1 1 PCOMMA_ 10B_VALUE_ 1 3 PMA_CDR_ SCAN_1 20 PMA_CDR_ SCAN_1 4 PRBS_ERR_ THRESHOLD _1 20 PRBS_ERR_ THRESHOLD _1 4 RX_XCLK_ SE...

Page 299: ...T_1 0 7 SATA_MIN_ INIT_1 4 TRANS_TIME_ FROM_P2_1 11 TRANS_ TIME_NON_ P2_1 11 TRANS_ TIME_TO_ P2_1 11 Do Not Modify TX_XCLK_ SEL_1 CLK_COR_ DET_LEN_ 1 1 CLK_COR_ PRECEDENCE _1 8 SATA_MIN_ INIT_1 3 TRAN...

Page 300: ...T_1 CHAN_ BOND_SEQ_ 2_2_1 1 7 CLK_COR_ SEQ_1_1_1 0 CLK_COR_ SEQ_1_3_1 4 CLK_COR_ SEQ_1_ ENABLE_1 3 CLK_COR_ SEQ_2_2_1 6 CLK_COR_ SEQ_2_3_1 0 COM_BURST _VAL_1 3 DEC_ PCOMMA_ DETECT_1 CHAN_ BOND_SEQ_ 2_...

Page 301: ...t Modify Do Not Modify PCS_COM_ CFG 22 6 CHAN_ BOND_SEQ_ 2_1_1 6 CHAN_ BOND_SEQ_ 1_4_1 8 CHAN_ BOND_SEQ_ 1_2_1 4 CHAN_ BOND_ MODE_1 0 Do Not Modify Do Not Modify Do Not Modify PCS_COM_ CFG 21 7 CHAN_...

Page 302: ...AN_ BOND_2_ MAX_SKEW_ 0 2 CHAN_ BOND_SEQ_ 1_1_0 1 CHAN_ BOND_SEQ_ 1_3_0 5 CHAN_ BOND_SEQ_ 1_ENABLE_0 4 3 PCS_COM_ CFG 8 TERMINATION_ CTRL 2 Do Not Modify Do Not Modify CHAN_ BOND_2_ MAX_SKEW_ 0 1 CHAN...

Page 303: ...Continued Bit Address 28 29 2A 2B 2C 2D 2E 2F Table D 9 DRP Addresses 30 through 37 Bit Address 30 31 32 33 34 35 36 37 0 CHAN_ BOND_SEQ_2 _2_0 9 MCOMMA_ 10B_VALUE_ 0 3 COMMA_ 10B_ENABLE _0 5 CLK_COR_...

Page 304: ..._0 4 13 MCOMMA_ 10B_VALUE_ 0 0 COMMA_ 10B_ENABLE _0 2 CLK_COR_ SEQ_2_ ENABLE_0 4 CLK_COR_ SEQ_2_3_0 5 CLK_COR_ SEQ_2_1_0 1 CLK_COR_ SEQ_1_4_0 3 CLK_COR_ SEQ_1_3_0 9 CLK_COR_ SEQ_1_1_0 5 14 MCOMMA_ 10B...

Page 305: ...Modify Do Not Modify TRANS_ TIME_TO_P2 _0 12 TRANS_ TIME_NON_ P2_0 12 TRANS_ TIME_FROM _P2_0 12 SATA_MIN_ INIT_0 5 10 CLK_COR_ MIN_LAT_ 0 1 CLK_COR_ ADJ_LEN_0 1 Do Not Modify Do Not Modify TRANS_ TIME...

Page 306: ...ND_SEQ_2 _3_0 3 7 SATA_MAX_ INIT_0 1 SATA_BURST _VAL_0 2 PRBS_ERR_ THRESHOLD _0 3 PRBS_ERR_ THRESHOLD _0 19 PMA_CDR_ SCAN_0 3 PMA_CDR_ SCAN_0 19 PCOMMA_ 10B_VALUE_ 0 2 CHAN_ BOND_SEQ_2 _3_0 2 8 SATA_M...

Page 307: ...Not Modify Do Not Modify Do Not Modify Do Not Modify Do Not Modify Do Not Modify 7 PMA_RX_ CFG_0 9 PMA_RX_ CFG_0 21 Do Not Modify Do Not Modify Do Not Modify Do Not Modify Do Not Modify Do Not Modify...

Page 308: ...308 www xilinx com Virtex 5 RocketIO GTP Transceiver User Guide UG196 v1 3 May 25 2007 Appendix D DRP Address Map of the GTP_DUAL Tile R...

Page 309: ...uffering Phase Alignment and Buffer Bypass page 102 Configurable RX Elastic Buffer and Phase Alignment page 161 Connecting TXUSRCLK and TXUSRCLK2 page 92 and Connecting RXUSRCLK and RXUSRCLK2 page 184...

Page 310: ...cled numbers in Figure E 2 Table E 1 GTP Transmitter Latency Block Number Block Name Latency TXDATAWIDTH 0 TXDATAWIDTH 1 1 Fabric Interface 1 5 cycles 2 cycles TXENC8B10BUSE 0 TXENC8B10BUSE 1 2 8B 10B...

Page 311: ...er 0 cycles 1 cycle RX_BUFFER_USE 0 RX_BUFFER_USE 1 11 RX FIFO 2 cycles 2 cycles CLK_COR_MIN_LAT RXCOMMADETUSE 0 RXCOMMADETUSE 1 8 Comma Alignment 2 cycles 2 4 cycles OVERSAMPLE_MODE FALSE OVERSAMPLE_...

Page 312: ...312 www xilinx com Virtex 5 RocketIO GTP Transceiver User Guide UG196 v1 3 May 25 2007 Appendix E Low Latency Design R...

Page 313: ...mind when designing a multi clock scheme Only one clock can be forwarded northbound through a tile at a time Only one clock can be forwarded southbound through a tile at a time A clock cannot be forw...

Page 314: ...fy write procedure to change the MUX selectors Figure F 1 Reference Clock Multiplexing Stucture Table F 1 MUX Selector REFCLK_SEL Bit Address REFCLK_SEL 0 6 0x04 REFCLK_SEL 1 5 0x04 REFCLK_SEL 2 4 0x0...

Page 315: ...ck to forward Clock 4 xx0 B Clock 2 1x1 0 Forward clock 2 northbound to tile A 1 Drive clock 3 southbound to tile C Clock 3 011 GTP_DUAL Tile Clock Muxing BUFG BUFR Clock 4 GREFCLK IBUFDS CLKP CLKIN G...

Page 316: ...0 Forward clock 1 northbound to tile C 0 Forward clock 2 southbound to tile E Clock 2 001 Clock 4 xx0 E Clock 1 1x1 0 Forward clock 1 northbound to tile D 0 Forward clock 2 southbound to tile F Clock...

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