Xilinx Virtex-4 FX FPGA, User Manual

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20 www.xilinx.com ML42 x User Guide
UG087 (v1.3) May 30, 2008
Detailed Description
R
The pin order in Table 15 is arranged from top to bottom as viewed on the board. It does
not reflect the physical connection to this connector.
57 AD16 AM22 AR26
59 AC16 AM21 AP26
61 AB15 AL19 AT24
63 AA15 AL18 AR24
Table 15: XGI Header (J11)
Pin Number ML421 ML423 ML424
1 IIC IIC IIC
2 IIC IIC IIC
3 U24 AG18 AP35
4 T24 AF18 AP34
5 Y16 AG16 AU26
6 Y15 AG17 AT26
7 W24 AF19 AT35
8 V24 AE17 AU35
9 AF14 AF21 AN20
10 AF13 AE21 AP20
11 AD15 AE16 AM22
12 AD14 AF16 AN22
13 AD13 AK29 AL19
14 AC14 AJ29 AL21
15 AC13 AK21 AK19
16 AC12 AL21 AJ19
17 AB12 AL29 AM21
18 AA12 AM30 AM20
19 TDO TDO TDO
20 X TDO X TDO X TDO
21 TCK TCK TCK
22 TMS TMS TMS
23 NC NC NC
24 VCC3 VCC3 VCC3
25 VCC3 VCC3 VCC3
Table 14: XGI Header (J13) (Continued)
Pin Number ML421 ML423 ML424
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