Xilinx Virtex-4 FX FPGA User Manual Download Page 23

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ML42

User Guide

www.xilinx.com

UG087 (v1.3) May 30, 2008

Detailed Description

H10

D10

M12

M11

AB11

AH14

AA11

AH13

AD12

AT15

AE12

AU15

AG13

AL13

AH13

AM13

AL8

AN8

AK8

AN7

AL10

AU10

AM10

AT10

AJ12

AP11

AK12

AR11

AK13

AK11

AL13

AJ11

AD14

AP16

AC13

AR16

Table 18:

LVDS Header (J139)

(Continued)

Pin Number

ML421

ML423

ML424

www.BDTIC.com/XILINX

Summary of Contents for Virtex-4 FX FPGA

Page 1: ...R ML42x User Guide Virtex 4 FX FPGA RocketIO Characterization Platform UG087 v1 3 May 30 2008 P N 0402349 02 www BDTIC com XILINX...

Page 2: ...T EXEMPLARY SPECIAL OR INCIDENTAL DAMAGES INCLUDING ANY LOSS OF DATA OR LOST PROFITS ARISING FROM YOUR USE OF THE DOCUMENTATION 2005 2008 Xilinx Inc All rights reserved XILINX the Xilinx logo the Bran...

Page 3: ...Ended SMA Clocks 15 5 Differential SMA MGT Clocks 15 6 Differential SMA Global Clocks 16 7 Differential SMA Regional Clocks 16 8 User LEDs Active High 16 9 User DIP Switches Active High 17 10 User Pus...

Page 4: ...4 www xilinx com ML42x User Guide UG087 v1 3 May 30 2008 R www BDTIC com XILINX...

Page 5: ...tions 16 Table 8 Differential SMA Regional Clock Pin Connections 16 Table 9 User LED Row 1 Top 16 Table 10 User LED Row 2 Bottom 17 Table 11 User DIP Switches Row 1 Top 17 Table 12 User DIP Switches R...

Page 6: ...6 www xilinx com ML42x User Guide UG087 v1 3 May 30 2008 R www BDTIC com XILINX...

Page 7: ...Virtex 4 family of FPGAs at http www xilinx com virtex4 includes Product highlights Data sheets User guides Application notes Additional information is available from the data sheets and application...

Page 8: ...e information Emphasis in text The address F is asserted after clock event 2 Underlined Text Indicates a link to a web page http www xilinx com virtex4 Convention Meaning or Use Example Blue text Cros...

Page 9: ...formation The ML42x product page contains the platform s current information including Current version of this user guide in PDF format Example design files for demonstration of Virtex 4 FPGA features...

Page 10: ...device under test or DUT in this user guide Onboard power supplies for all necessary voltages capable of supplying 1 5A to 6A Power supply jacks for optional use of external power supplies JTAG config...

Page 11: ...T_RX_LEFT Jack MGT_VTT_RX_RIGHT Jack MGT_VTT_TX_LEFT Jack MGT_VTT_TX_RIGHT Jack AVCCAUX_TX Jack AVCCAUX_RX Jack AVCCAUXMGT Jack MGT_VREF Jack 1 5V 2 5V 1 5V 2 5V 2 5V 1 2V LVDS UG087_01_092006 Virtex...

Page 12: ...the numbered sections that follow Note The image might not reflect the current revision of the board Figure 2 Detailed Description of Virtex 4 FPGA ML42x Platform Components 4 19 11 1 4 21 20 13 15 16...

Page 13: ...n the board Onboard Regulation The ML42x platform has onboard regulation for the DUT main power supplies listed in Table 2 These regulators also have a corresponding input voltage jack to supply each...

Page 14: ...sed through the onboard System ACE controller Note The System ACE controller is bypassed when the flying wire leads or the Parallel Cable IV cable is used thus causing no disruption in the JTAG chain...

Page 15: ...5 5 Differential SMA MGT Clocks The ML42x platform has four pairs of LVDS differential SMA MGT clock inputs as shown in Table 6 These are dedicated clock inputs for RocketIO transceivers Table 4 OSC...

Page 16: ...se SMAs can also be used as single ended clock inputs 8 User LEDs Active High Twenty active High LEDs shown in Table 9 and Table 10 page 17 are connected to user I O pins on the FPGA These LEDs can be...

Page 17: ...ates DS17 N4 AH7 AU7 DS18 M4 AH8 AU8 DS19 AB9 AJ15 AH12 DS20 P3 AK9 AR9 Table 10 User LED Row 2 Bottom Label Pin ML421 ML423 ML424 DS31 V4 AH9 AK9 DS29 U4 AJ9 AL9 DS28 T3 AD9 AN9 DS32 T4 AD10 AP9 DS33...

Page 18: ...AR12 7 U5 AM13 AP12 8 U6 AH12 AT13 9 AA8 AF9 AL11 10 AA9 AG11 AR13 Table 12 User DIP Switches Row 2 Bottom SW6 Pin ML421 ML423 ML424 1 N3 AL9 AT9 2 Y8 AK7 AR7 3 Y7 AB12 AU16 4 T9 AA13 AU17 5 AA7 AL14...

Page 19: ...d to this connector Table 14 XGI Header J13 Pin Number ML421 ML423 ML424 1 U19 AC23 AU25 3 T18 AC22 AT25 5 AA17 AE22 AR27 7 Y17 AD22 AP27 9 AA20 AF25 AN30 11 AA19 AF24 AP30 13 AB22 AG25 AL30 15 AB21 A...

Page 20: ...umber ML421 ML423 ML424 1 IIC IIC IIC 2 IIC IIC IIC 3 U24 AG18 AP35 4 T24 AF18 AP34 5 Y16 AG16 AU26 6 Y15 AG17 AT26 7 W24 AF19 AT35 8 V24 AE17 AU35 9 AF14 AF21 AN20 10 AF13 AE21 AP20 11 AD15 AE16 AM22...

Page 21: ...VCC5 31 VCC5 VCC5 VCC5 32 VCC5 VCC5 VCC5 Table 16 XGI Header J10 Pin Number ML421 ML423 ML424 1 32 VCCO VCCO VCCO Table 17 XGI Header J14 Pin Number ML421 ML423 ML424 2 E20 G22 J27 4 D20 H22 K27 6 E22...

Page 22: ...ated by the user 36 J21 F24 L29 38 G21 D25 J30 40 F22 C25 H30 42 H24 E27 E31 44 G24 D27 D31 46 J23 G25 D29 48 K23 F25 C29 50 L24 K26 G31 52 M24 J26 F31 54 N24 K24 G33 56 N23 L24 G32 58 M22 P24 C33 60...

Page 23: ...30 M12 E3 32 M11 F3 34 AB11 AH14 36 AA11 AH13 38 AD12 AT15 40 AE12 AU15 42 AG13 AL13 44 AH13 AM13 46 AL8 AN8 48 AK8 AN7 50 AL10 AU10 52 AM10 AT10 54 AJ12 AP11 56 AK12 AR11 58 AK13 AK11 60 AL13 AJ11 62...

Page 24: ...s the System ACE controller 15 DONE LED The DONE LED indicates the status of the DONE pin of the FPGA This LED lights when DONE is High indicating the FPGA is programed or that power is applied to the...

Page 25: ...le 20 19 RocketIO Transceiver Pins All RocketIO transceiver pins are connected to differential SMA pairs The RocketIO transceiver pins are shown in Table 21 which spans multiple pages Table 20 Bitstre...

Page 26: ...D39 J149 TXP_104A AC39 J155 RXN_104A AA39 J148 RXP_104A Y39 J152 RXN_104B X0Y4 AJ39 J151 RXP_104B AH39 J153 TXN_104B AF39 J150 TXP_104B AE39 J94 TXN_105A X0Y1 X0Y1 X0Y3 X0Y3 X0Y3 AC26 AK34 AR39 J89 TX...

Page 27: ...X1Y3 X1Y3 X1Y3 AF3 AG1 AR1 J42 TXP_110A AF2 AF1 AP1 J44 RXN_110A AD1 AD1 AM1 J43 RXP_110A AC1 AC1 AL1 J41 RXN_110B X1Y0 X1Y0 X1Y2 X1Y2 X1Y2 AF8 AM1 AW4 J48 RXP_110B AF7 AL1 AW3 J46 TXN_110B AF5 AJ1 AU...

Page 28: ...A8 J53 RXP_113A A4 A7 A9 J49 RXN_113B X1Y2 X1Y4 X1Y6 X1Y6 X1Y8 H1 G1 D1 J59 RXP_113B G1 F1 C1 J56 TXN_113B E1 D1 A3 J55 TXP_113B D1 C1 A4 J118 TXN_114A X1Y9 X1Y11 A14 A15 J117 TXP_114A A15 A16 J115 RX...

Page 29: ...otentiometers are labeled RTERM 105 and RTERM 110 Through a master slave bias circuit these externally controlled biases can be shared across all MGT tiles within the MGT column For more information o...

Page 30: ...e 2 UG070 Virtex 4 FPGA User Guide 3 DS080 System ACE CompactFlash Solution 4 UG091 Xilinx Generic Interface XGI SuperClock Module User Guide Table 23 System ACE Port Connections Pin Name ML421 ML423...

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