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Copyright

© Copyright 2021 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, Kintex, Kria, Spartan, Versal,
Vitis, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx
in the United States and other countries. PCI, PCIe, and PCI Express are trademarks of PCI-SIG
and used under license. All other trademarks are the property of their respective owners.

Appendix C: Additional Resources and Legal Notices

UG1518 (v1.0) December 17, 2021

 

www.xilinx.com

T1 Telco Accelerator Card Installation Guide

 48

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Summary of Contents for T1

Page 1: ...removing non inclusive language from our products and related collateral We ve launched an internal initiative to remove language that could exclude people or reinforce historical biases including ter...

Page 2: ...16 T1 Skeleton Design on the ZU19 Zynq UltraScale MPSoC 16 T1 Skeleton Design on the ZU21 Zynq UltraScale RFSoC 17 T1 Skeleton Design Package 18 Chapter 6 Running the Tests 20 100G Internal Connectio...

Page 3: ...ix B Regulatory Compliance Statements 43 FCC Class A Products 43 Safety 43 EMC Compliance 44 FCC Class A User Information 44 VCCI Class A Statement 45 Appendix C Additional Resources and Legal Notices...

Page 4: ...tor card is a PCI Express PCIe Gen3 x16 compliant card featuring the 16 nm Zynq UltraScale MPSoC and Zynq UltraScale RFSoC devices The T1 form factor is full height half length FHHL and single slot wi...

Page 5: ...inux 64 bit CentOS 7 and 8 Ubuntu 16 18 and 20 System memory and CPU cores For deployment installations a minimum of 16 GB plus application memory requirements is required For development installation...

Page 6: ...These steps are for a single T1 card deployment 1 Power on the server The output on the monitor is shown below 2 Wait until the monitor lists the shortcut keys so you can navigate into the setup The...

Page 7: ...S option as shown below 5 Select Integrated Devices 6 In the menu that is displayed scroll down until you get to Slot Bifurcation It is on the second half of the page Chapter 1 Introduction UG1518 v1...

Page 8: ...or x8 Bifurcation This enables the T1 card in the slot with the correct communication over the PCI Click the Back button in the lower right hand side of the screen Chapter 1 Introduction UG1518 v1 0 D...

Page 9: ...es to save the changes you made 12 Click the Finish button again 13 When the system has rebooted check to see if the T1 card has been detected using the lspci grep Xilinx command If the card has been...

Page 10: ...Chapter 1 Introduction UG1518 v1 0 December 17 2021 www xilinx com T1 Telco Accelerator Card Installation Guide 10 Send Feedback...

Page 11: ...strap to an unpainted metal surface on the chassis Avoid touching the card with your clothing The wrist strap protects components from ESD on the body only Handle the card by its bracket or edges only...

Page 12: ...ou are working with an enclosed computer open your computer by removing the casing 3 If necessary remove the adjacent PCIe slot cover corresponding to the PCIe slot in which you are installing the car...

Page 13: ...n design package along with a script to ensure that the software is installed correctly The package and the scripts are described in the T1 Skeleton Design Package section of this document The demos p...

Page 14: ...SB cable and Xilinx tools is described in Appendix A Programming the Devices Using JTAG The following sections describe how to set up the flash_app code to program the QSPI that is connected to the ZU...

Page 15: ...t time execute sc_flash sh image_name bsl_password_file The expected output is as follows Please reboot the Host and re run the command 4 Reboot the host 5 Program the SC image For the second time exe...

Page 16: ...o working only in even numbered PCIe slots If you use an odd numbered slot designs can be loaded into the devices but the tests described in Chapter 6 Running the Tests do not run T1 Skeleton Design o...

Page 17: ...the PCIe Gen3 x8 from the host to the different parts of the ZU21 These connections are accomplished through AXI interconnect These connections are as follows Processing system and its DDR PL DDR thr...

Page 18: ...es as a Git repository The code is stored in different branches with one separate branch for each supported DPDK version 18 11 19 11 and 20 11 Figure 4 Git Branch Structure Chapter 5 T1 Skeleton Desig...

Page 19: ...d to run the design test sh This script is used to run all the tests described in Chapter 6 Running the Tests When you have downloaded the package select the branch for the correct DPDK version then r...

Page 20: ...1 25G_2 25G_3 PS DDR 2G DDR 4G DDR 4G DDR 2G SFP X25234 033121 The following section describes each test including setup running and expected results The primary objective of testing is to verify the...

Page 21: ...y in the Zynq UltraScale MPSoC and Zynq UltraScale RFSoC devices Data transferred from the Zynq UltraScale MPSoC reaches the Zynq UltraScale RFSoC through this internal interface and vice versa Test P...

Page 22: ...When the test is complete stop traffic with the command stop all and then quit the test 8 Repeat these steps for lanes 2 4 changing the argument to l2 l3 and l4 respectively The expected results runn...

Page 23: ...re the conditions in the Chapter 2 Card Information and Installation section have been met 4 Run the test sh in root with init as argument to initialize the DMA and DPDK drivers 5 Execute the test sh...

Page 24: ...TX of the pktgen application There should not be any packet loss RX and TX counts should be identical There should be no mismatch in TX and RX packets Chapter 6 Running the Tests UG1518 v1 0 December...

Page 25: ...238 033121 2 Ensure the conditions in the Chapter 2 Card Information and Installation section have been met 3 Run the test sh in root with init as argument to initialize the DMA and DPDK drivers 4 Exe...

Page 26: ...pktgen application There should not be any packet loss RX and TX counts should be identical There should not be any mismatch in TX and RX packets Chapter 6 Running the Tests UG1518 v1 0 December 17 20...

Page 27: ...39 033121 2 Ensure the conditions in the Chapter 2 Card Information and Installation section have been met 3 Run the test sh in root with init as argument to initialize the DMA and DPDK drivers 4 Exec...

Page 28: ...pktgen application There should not be any packet loss RX and TX counts should be identical There should not be any mismatch in TX and RX packets Chapter 6 Running the Tests UG1518 v1 0 December 17 20...

Page 29: ...d Write Test Setup Dell PowerEdge R740 Server QDMA Poll Mode Driver PCIe x16 Xilinx T1 Telco Card MPSoC PCIe x8 PS RFSoC PCIe x8 PS DDR 2G DDR 4G DDR 4G DDR 2G QDMA Test Application X25235 033121 Test...

Page 30: ...H2C text file size 0 7 Confirm if the DMA transfer is successful An example based on the example files in step 2 is as follows dma_to_device 0 1 dma_test_input txt 1073741824 13 0 The second test aga...

Page 31: ...nts Contents of the text files for H2C and C2H should match after DMA transfers Chapter 6 Running the Tests UG1518 v1 0 December 17 2021 www xilinx com T1 Telco Accelerator Card Installation Guide 31...

Page 32: ...The QMDA test application guide is available here The address map used in the tests in this document is shown in the following figure Figure 7 Address Map Chapter 6 Running the Tests UG1518 v1 0 Dece...

Page 33: ...n this document is a starting point You can also start a design from scratch using the development tools located at the Xilinx Design Tools web page For more information about the T1 Telco accelerator...

Page 34: ...PSoC but not for Zynq UltraScale RFSoC It works in SDK 2019 1 for both Zynq UltraScale MPSoC and Zynq UltraScale RFSoC Dynamic configuration of the FPGA bit file over PCAP might not work as expected a...

Page 35: ...G using an ADK connector The Xilinx tools must be installed on a computer and then connected to the T1 card through an ADK connector An ADK connector is not part of the T1 card and must be obtained se...

Page 36: ...ard then connect the ADK card to a micro USB cable so that it can connect to a computer that can run the Xilinx tools The full connection is shown below Appendix A Programming the Devices Using JTAG U...

Page 37: ...the back of the server This setup allows the USB to be connected to an external laptop running on the server The Xilinx tools can be on the laptop or the server to program the devices on the T1 card...

Page 38: ...SoC QSPI Using SDK The following describes using the how to use the Xilinx tools to program the QSPIs on the T1 card Note If you use this method the Xilinx tools must be loaded on the server and it is...

Page 39: ...ram Flash wizard browse to and select the boot bin image file that was created for the Zynq UltraScale MPSoC 6 Select the auto detect option in the target device Zynq UltraScale MPSoC will be selected...

Page 40: ...connected is shown in the previous section outside of a server 2 In Xilinx SDK create a new hardware project using the Zynq UltraScale RFSoC HDF file 3 In Xilinx SDK select Xilinx Tools Program Flash...

Page 41: ...med directly using the Vivado Design Suite Make sure you have installed Vivado before proceeding with the steps below IMPORTANT When you install Vivado and then perform a cold boot of the servers the...

Page 42: ...ings in the slot using the BIOS in the iDRAC GUI you might also need to change the PCIe settings in the Console during the restart 5 Perform a warm reboot on the host machine Appendix A Programming th...

Page 43: ...y The following safety standards apply to all products listed in this document IEC 62368 1 2nd Edition 2014 A11 2017 Information technology equipment Safety Part 1 General requirements EN 62368 1 2nd...

Page 44: ...found to comply with the limits for a Class A digital device pursuant to Part 15 of the FCC rules These limits are designed to provide reasonable protection against harmful interference when the equip...

Page 45: ...VCCI Class A Statement Appendix B Regulatory Compliance Statements UG1518 v1 0 December 17 2021 www xilinx com T1 Telco Accelerator Card Installation Guide 45 Send Feedback...

Page 46: ...ign Tools DocNav At the Linux command prompt enter docnav Xilinx Design Hubs provide links to documentation organized by design tasks and other topics which you can use to learn key concepts and addre...

Page 47: ...distribute or publicly display the Materials without prior written consent Certain products are subject to the terms and conditions of Xilinx s limited warranty please refer to Xilinx s Terms of Sale...

Page 48: ...in are trademarks of Xilinx in the United States and other countries PCI PCIe and PCI Express are trademarks of PCI SIG and used under license All other trademarks are the property of their respective...

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