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Xilinx ML630, User Manual

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Xilinx ML630 User Manual Download Page 12

ML630 Board User Guide

www.xilinx.com

11

UG828 (v1.0) September 28, 2011

Detailed Description

32. P3, J3 FCI Airmax Interlaken plug and receptacle connectors

33. J3 refclk (J132, J133) SMA connectors

34. P2, J2 FCI Airmax Interlaken plug and receptacle connectors

FPGA U2 FCI Airmax Interlaken Connectors

35. P4, J4 FCI Airmax Interlaken plug and receptacle connectors

36. J4 refclk (J134, J135) SMA connectors

FPGA U1 and FPGA U2 Clock Circuits

37. Differential clock input connectors CLK0 SMA (J167, J168) with 1-to-2 3.3V LVPECL 

buffer (U98)

38. Differential clock input connectors CLK1 SMA (J169,J170) with 1-to-2 3.3V LVPECL 

buffer (U99) 

39. Differential clock input connectors CLK2 SMA (J171, J172) with 1-to-2 3.3V LVPECL 

buffer (U96) 

40. Differential clock input connectors CLK3 SMA (J9, J10) with 1-to-2 3.3V LVPECL buffer 

(U97)

41. Four I

2

C programmable Silicon Labs Si570 3.3V LVPECL 10 MHz-to-810 MHz 

oscillators (U43, U44, U51, U52) each with a 1-to-2 3.3V LVPECL buffer (U53, U54, U55, 
U56, bottom of board) 

42. Two differential clock input-output 8x8 crosspoint switches (U57, U58)

43. FPGA U1 differential test clock input SMA connectors (J124, J125) with 1-to-6 3.3V 

LVDS buffer (U126)

44. FPGA U2 differential test clock input SMA connectors (J126, J127) with 1-to-6 3.3V 

LVDS buffer (U127)

45. Six dual 2-to-1 3.3V LVDS input, 3.3V LVPECL output differential clock multiplexers 

(U102, U115, U116, U120, U121, U122)

46. Two I

2

C programmable Silicon Labs Si570 3.3V LVPECL 10 MHz-to-810 MHz 

oscillators, one for FPGA U1 (U64) and one for FPGA U2 (U65) (bottom of board), each 
with a 1-to-6 3.3V LVDS buffer (U13, U18), top of board) 

ML630 I

2

C Bus

47. I

2

C Main Bus: M24C02 256x8 EEPROM (U59), TI PCA9548 (U31) 1-to-8 port I

2

C 

expander (six ports wired to the Si570 oscillators, two ports wired to the 8x8 crosspoint 
switches); U1 I

2

C: HPC FMC1 J290; U2 I

2

C: HPC FMC2 J104

ML630 HPC FMC Connectors

48. FMC1 connector (J290)

49. FMC2 connector (J104)

Default Jumper Positions

A list of shunts and their required positions for normal board operation is provided in 

Appendix A, Default Jumper Positions

.

Summary of Contents for ML630

Page 1: ...ess mainly focus on the distribution of electronic components Line cards we deal with include Microchip ALPS ROHM Xilinx Pulse ON Everlight and Freescale Main products comprise IC Modules Potentiometer IC Socket Relay Connector Our parts cover such applications as commercial industrial and automotives areas We are looking forward to setting up business relationship with you and hope to provide you...

Page 2: ...ML630 Virtex 6 HXT FPGA Optical Transmission Network Evaluation Board User Guide UG828 v1 0 September 28 2011 ...

Page 3: ... reasonably foreseeable or Xilinx had been advised of the possibility of the same Xilinx assumes no obligation to correct any errors contained in the Materials or to advise you of any corrections or update You may not reproduce modify distribute or publicly display the Materials without prior written consent Certain products are subject to the terms and conditions of the Limited Warranties which c...

Page 4: ...O 10 FPGA U2 Indicators and I O 10 FPGA U1 FCI Airmax Interlaken Connectors 10 FPGA U2 FCI Airmax Interlaken Connectors 11 FPGA U1 and FPGA U2 Clock Circuits 11 ML630 I2 C Bus 11 ML630 HPC FMC Connectors 11 Default Jumper Positions 11 Monitoring Voltage and Current 12 References 12 FPGA U1 and U2 12 References 12 Board Power and Switch 12 Disabling FPGA Onboard Power 16 FPGA Configuration 16 Syste...

Page 5: ... U2 41 FPGA U1 and U2 Differential SMA Clock Inputs 42 Differential 2 5V Si570 LVDS Oscillators 43 Differential SN65LVCP408PAP 8X8 Crosspoint switches 43 FPGA U1 Differential SMA Test Clock Inputs 44 FPGA U2 Differential SMA Test Clock Inputs 45 FPGA U1 and U2 Si570 with 1 to 6 Clock Buffer Two Circuits 45 FPGA U1 and U2 Example GTH Clock Routing Example 47 Setup of U1 and U2 GTH Bank 106 and 107 ...

Page 6: ...ists the jumpers that must be installed on the board for proper operation Appendix B VITA 57 1 FMC HPC Connector Pinout provides a pinout reference for the FPGA mezzanine card FMC connectors Appendix C ML630 Master UCF Listing for U1 provides a listing of the ML630 FPGA U1 user constraints file UCF Appendix D ML630 Master UCF Listing for U2 provides a listing of the ML630 FPGA U2 user constraints ...

Page 7: ...ctical statement ngdbuild design_name Helvetica bold Commands that you select from a menu File Open Keyboard shortcuts Ctrl C Italic font Variables in a syntax statement for which you must supply values ngdbuild design_name References to other manuals See the Command Line Tools User Guide for more information Emphasis in text If a wire is drawn so that it overlaps the pin of a symbol the two nets ...

Page 8: ...m ACE controller with companion CompactFlash socket General purpose pushbutton and DIP switches LEDs and test I O header for each FPGA VGA 2X5 male debug header for each FPGA USB to UART bridge with USB Mini B pcb connector for each FPGA Two VITA 57 1 FMC HPC connectors I2 C bus hosting EEPROM clock sources and FMC connectors A separate SiTime fixed 200 MHz 2 5V LVDS oscillator wired to each FPGAs...

Page 9: ...n the sections that follow Note The image in Figure 1 2 is for reference only and might not reflect the current revision of the board X Ref Target Figure 1 1 Figure 1 1 ML630 Board Block Diagram UG828_c1_01_091211 Header Receptacle Receptacle USB SystemACE 10 Pin Debug Port Si570 Si570 10 Pin Debug Port 4 I2C Programmable Oscillators 8 in 16 Diff Out Crosspoint Switch To GTX GTH HX565T FF1924 HX56...

Page 10: ...141 and J102 FPGA Power Inhibit Jumper 6 J289 regulator inhibit jumper FPGA U1 and U2 Power System Controllers 7 U1 and U2 TI UCD9240 digital power controllers U8 U19 U32 and U77 8 PMBus connector J7 for TI GPIO adapter PMBus pod X Ref Target Figure 1 2 Figure 1 2 Detailed Description of ML630 Board Components UG828_c1_02_080411 16 17 18 29 49 48 19 27 22 26 21 14 13 7 9 12 15 7 11 10 30 2 45b 45a...

Page 11: ... SystemACE reset pushbutton SW2 20 SystemACE C F image select DIP switch SW3 FPGA U1 Indicators and I O 21 U1 PROG pushbutton SW5 INIT LED DS20 and DONE LED DS6 22 U1 User LEDs DS10 DS17 User DIP switch SW7 and user pushbutton switches SW4 SW6 SW8 SW9 23 23a U1 User GPIO 2X6 header J285 23b VGA video debug 2x5 header J16 24 U1 USB UART Mini B connector J54 top of board and USB to UART bridge IC U2...

Page 12: ...ach with a 1 to 2 3 3V LVPECL buffer U53 U54 U55 U56 bottom of board 42 Two differential clock input output 8x8 crosspoint switches U57 U58 43 FPGA U1 differential test clock input SMA connectors J124 J125 with 1 to 6 3 3V LVDS buffer U126 44 FPGA U2 differential test clock input SMA connectors J126 J127 with 1 to 6 3 3V LVDS buffer U127 45 Six dual 2 to 1 3 3V LVDS input 3 3V LVPECL output differ...

Page 13: ...luded with the board Power can also be provided through J141 and J102 ATX hard disk type 4 pin power connectors The DIN4 J122 and ATX J141 connectors are wired in parallel as are J75 and J102 Note Use of a switchable power bar multiple outlet power strip is recommended for the two ML630 AC adapters The two adapters can then be turned on and off simultaneously via the power bar on off switch Cautio...

Page 14: ...age 53 U1_VCCINT 1 00V U1_VCCAUX 2 50V U2_VCCINT 1 00V U2_VCCAUX 2 50V U1_MGTHAVCC 1 10V PTD08A006W U1 MGTHAVCCRX 1 10V 6A max U1_MGTHAVCCRX 1 10V PTD08A006W U1 MGTHAVTT 1 20V 6A max U1_MGTHAVTT 1 20V PTD08A006W U1 MGTHAVCCPL 1 80V 6A max UCD9240 PMBus Controller Addr54 U1_MGTHAVCCPLL 1 80V PTD08A010W U1 MGTXAVCC 1 10V 10A max U1_MGTXAVCC 1 10V PTD08A006W U1 MGTXAVTT 1 20V 6A max U1_MGTXAVTT 1 20V...

Page 15: ... FPGA U2 Power Block Diagram UG828_c1_04_081211 Balance of U2 Power System Pages 103 109 On Off Slide Soft SW1 Page 53 J105 U2 12V Fan Power Circuit 103 UCD9240 PMBus Controller Addr55 U77 105 PTD08A010W U2 MGTHAVCC 1 10V 10A max CH 1A 106 PTD08A006W U2 MGTHAVCCRX 1 10V 6A max CH 2A 107 PTD08A006W U2 MGTHAVTT 1 20V 6A max CH 3A 108 PTD08A006W U2 MGTHAVCCPLL 1 80V 6A max CH 4A 109 103 J75 DIN4 12V ...

Page 16: ...em controller address 53 PTD08A010W U3 Adjustable switching regulator 10A 0 6V to 3 6V U1_MGTHAVCC 1 1V PTD08A006W U14 Adjustable switching regulator 6A 0 6V to 3 6V U1_MGTXAVCCRX 1 1V PTD08A006W U20 Adjustable switching regulator 6A 0 6V to 3 6V U1_MGTHAVTT 1 2V PTD08A006W U21 Adjustable switching regulator 6A 0 6V to 3 6V U1_MGTXAVCCPLL 1 8V U1 and U2 GTX Voltage Controller and Regulators UCD924...

Page 17: ...card plugged into socket U46 see Table 1 2 page 17 Upon power on the System ACE controller checks for the presence of a flash card and loads the FPGA configuration files from it if present The JTAG chain of the board is illustrated in Figure 1 5 Each component except the System ACE IC with a JTAG interface has a bypass jumper which permits the component to be in the chain or bypassed System ACE Co...

Page 18: ...0 System ACE CompactFlash Solution FPGA U1 PROG Pushbutton INIT LED and DONE LED Figure 1 2 callout 21 Pressing the U1 PROG push button SW5 grounds the active Low program pin of the FPGA The INIT LED DS20 lights during FPGA initialization The DONE LED DS56 indicates the state of the DONE pin of the FPGA When the DONE pin is High the DONE LED lights indicating that the FPGA is successfully configur...

Page 19: ...des a set of eight active High switches that are connected to user I O pins on the FPGA as shown in Table 1 4 These switched signals can be used to set control bits or any other purpose determined by the user Table 1 3 FPGA U1 User LEDs FPGA U1 Pin Net Name Reference Designator K33 U1_USER_LED1 DS17 L33 U1_USER_LED2 DS16 A37 U1_USER_LED3 DS15 B37 U1_USER_LED4 DS14 B36 U1_USER_LED5 DS13 B35 U1_USER...

Page 20: ...unications between the ML630 board FPGA U1 and a host computer are accomplished through a USB cable connected to J54 Control is provided by U26 a USB to UART bridge Silicon Laboratories CP2103 Table 1 7 lists the pin assignments and signals for the USB connector J54 Table 1 5 FPGA U1 User Pushbuttons FPGA U1 Pin Net Name Reference Designator H26 U1_USER_PB1 SW4 J26 U1_USER_PB2 SW6 N24 U1_USER_PB3 ...

Page 21: ...B to UART bridge to appear as a COM port to the host computer communications application software for example HyperTerminal or TeraTerm The VCP driver must be installed on the host computer prior to establishing communications with the ML630 board References More information on the Silicon Labs CP2103 USB to UART bridge is available at http www silabs com products interface usbtouart Pages default...

Page 22: ... during FPGA initialization The DONE LED DS29 indicates the state of the DONE pin of the FPGA When the DONE pin is High the DONE LED lights indicating that the FPGA is successfully configured FPGA U2 User LEDs DIP and Pushbutton Switches Figure 1 2 callout 27 DS30 through DS35 DS37 and DS38 are eight active High LEDs that are connected to user I O pins on FPGA U2 as shown in Table 1 11 These LEDs ...

Page 23: ...ser Push Buttons Active High Figure 1 2 callout 27 SW12 SW13 SW14 and SW15 are active High user pushbuttons that are connected to user I O pins on FPGA U2 as shown in Table 1 13 These switches can be used for any purpose determined by the user Table 1 12 FPGA U2 User DIP Switches FPGA U2 Pin Net Name Reference Designator J20 U2_USER_SW1 SW16 K21 U2_USER_SW2 P21 U2_USER_SW3 R21 U2_USER_SW4 G20 U2_U...

Page 24: ...e range of 2 5V on the ML630 board The connections between FPGA U2 and CP2103 should use the LVCMOS25 I O standard UART IP for example Xilinx XPS UART Lite must be implemented in the FPGA logic FPGA U2 supports the USB to UART bridge using four signal pins Transmit TX Receive RX Request to Send RTS Clear to Send CTS Connections of these signals between the FPGA and the CP2103 at U79 are listed in ...

Page 25: ...uart Pages default aspx FPGA U2 200 MHz 2 5V LVDS Oscillator Figure 1 2 callout 30 Oscillator U63 located on the bottom of the board is connected to FPGA U2 global clock inputs Table 1 18 lists FPGA U2 pin connections to the LVDS oscillator U63 References More information on the SiTime SI9102AI oscillator is available at http www sitime com products differential oscillators sit9102 Table 1 16 FPGA...

Page 26: ...ng documents located on the Interlaken Alliance website http www interlakenalliance com Protocol Interlaken Protocol Definition v1 x and Connector Pinouts Interlaken Interop Recommendations v1 x The Protocol Definition document also discusses the flow control functions provided by the TX and RX FC_CLK FC_DATA and FC_SYNC connector pins Three sets of connector pairs P1 J1 P2 J2 and P3 J3 are wired ...

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