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Xilinx ML410, User Manual

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ML410 Embedded Development Platform

www.xilinx.com

77

UG085 (v1.7.2) December 11, 2008

Detailed Description

R

Table 2-40

shows the output combinations of the clock multiplexer.

Front Panel Interface (J23)

The front panel interface connector (J23) is a 24-pin header that accepts a standard IDC 24
pin connector (0.1 inch pitch). J23 provides an optional means to control and gather status
information from the ML410 if enclosed in a case similar to a desktop computer. The
functionality listed below can easily be connected with a custom user-provided cable that
connects to user logic designed to control and monitor the functionality available through
the front panel interface.

The front panel interface provides the following control capability:

♦

Power ON|OFF the board

-

ML410 platforms are delivered with a jumper installed on J23

♦

Eight System ACE configuration selections

-

Connects to the three System ACE configuration address lines

♦

System ACE Reset

-

Active-Low input (pulsed)

♦

CPU Reset

-

Active-Low input (pulsed)

The front panel interface provides access to the following status information:

♦

FPGA configuration DONE output

♦

IDE disk access output

♦

ATX power output

♦

Two FPGA user-defined output signals

♦

ATX speaker output

♦

Keyboard inhibit input (active-Low)

Note:

All front panel interface outputs, except for the speaker out, can drive LEDs.

Table 2-40:

Outputs of the Clock Multiplexer (U6)

CLK_SEL0 CLK_SEL1

Q0

Q1

0

0

250 MHz MGTCLK sourced
from X5

250 MHz SGMIICLK sourced
from X5

0

1

250 MHz MGTCLK sourced
from X5

SGMIICLK sourced from the
MGT SMA connectors at J20
and J21

1

0

MGTCLK sourced from the
MGT SMA connectors at J20
and J21

250 MHz SGMIICLK sourced
from X5

1

1

MGTCLK sourced from the
MGT SMA connectors at J20
and J21

SGMIICLK sourced from the
MGT SMA connectors at J20
and J21

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Summary of Contents for ML410

Page 1: ...R ML410 Embedded Development Platform User Guide UG085 v1 7 2 December 11 2008 Downloaded from Elcodis com electronic components distributor...

Page 2: ...N 2006 2008 Xilinx Inc All rights reserved XILINX the Xilinx logo the Brand Window and other designated brands included herein are trademarks of Xilinx Inc PowerPC is a trademark of IBM Corp and is us...

Page 3: ...ation and Configuration 18 Board Level Integration 18 Embedded Development Kit 19 EDK Components 19 Platform Studio Features 19 Chapter 2 ML410 Embedded Development Platform Overview 21 Features 21 Bl...

Page 4: ...Controller 66 AC 97 Audio Interface 67 PS 2 Keyboard and Mouse Interface Connector P2 68 Flash ROM U4 68 IIC SMBus Interface 69 Introduction to IIC SMBus 69 IIC SMBus Signaling 69 IIC SMBus on ML410 P...

Page 5: ...ML410 Embedded Development Platform www xilinx com 5 UG085 v1 7 2 December 11 2008 R Appendix A Board Revisions Appendix B References Downloaded from Elcodis com electronic components distributor...

Page 6: ...6 www xilinx com ML410 Embedded Development Platform UG085 v1 7 2 December 11 2008 R Downloaded from Elcodis com electronic components distributor...

Page 7: ...ug Connector Pinout 51 Figure 2 15 CPU JTAG Header J12 53 Figure 2 16 PCI Express Power Management and Clocking 55 Figure 2 17 PCI Bus and Device Connectivity 58 Figure 2 18 ALi South Bridge Interface...

Page 8: ...8 www xilinx com ML410 Embedded Development Platform UG085 v1 7 2 December 11 2008 R Downloaded from Elcodis com electronic components distributor...

Page 9: ...46 Table 2 15 System ACE MPU Connection from FPGA to Controller 46 Table 2 16 GPIO LED Connection from FPGA to U36 49 Table 2 17 GPIO LCD Data Signals from FPGA to U35 49 Table 2 18 GPIO LCD Control S...

Page 10: ...Front Panel Interface Connector J23 78 Table 2 42 5V Fan BERG Header Connections 79 Table 2 43 Voltage Margining Jumper Settings 80 Table 2 44 Voltage Monitor Information 83 Table 2 45 Delay Offsets...

Page 11: ...ent platform and details the components and features of the ML410 board Appendix A Board Revisions details the differences between board revisions in the ML410 series Appendix B References Additional...

Page 12: ...e information Emphasis in text If a wire is drawn so that it overlaps the pin of a symbol the two nets are not connected Square brackets An optional entry or parameter However in bus specifications su...

Page 13: ...ross reference link to a location in another document See Figure 2 5 in the Virtex II Platform FPGA User Guide Blue underlined text Hyperlink to a website URL Go to http www xilinx com for the latest...

Page 14: ...14 www xilinx com ML410 Embedded Development Platform UG085 v1 7 2 December 11 2008 Preface About This Guide R Downloaded from Elcodis com electronic components distributor...

Page 15: ...m copper process using 300 mm 12 inch wafer technology Combining a wide variety of flexible features the Virtex 4 family enhances programmable logic design capabilities and is a powerful alternative t...

Page 16: ...vel 1 instruction cache and 16 KB level 1 data cache Integrated level 1 cache parity generation and checking CoreConnect bus architecture Efficient high performance on chip memory OCM interface to blo...

Page 17: ...ion tools available for programmable logic design along with design entry synthesis and verification capabilities With its ultra fast runtimes an average 40 faster than the nearest competitive FPGA of...

Page 18: ...on Programmable logic design implementation assigns the logic created during design entry and synthesis into specific physical resources of the target device The term place and route has historically...

Page 19: ...o XPS is a graphical user interface technology that integrates all of the processes from design entry to design debug and verification XPS streamlines development with the embedded features of the Xil...

Page 20: ...20 www xilinx com ML410 Embedded Development Platform UG085 v1 7 2 December 11 2008 Chapter 1 Introduction to Virtex 4 ISE and EDK R Downloaded from Elcodis com electronic components distributor...

Page 21: ...of the ML410 using the applications contained on the CompactFlash card The reference designs were produced using the Xilinx Embedded Development Kit EDK ISE and Answer Browser solution records Tutoria...

Page 22: ...I O GPIO Flash memory interface Two serial ATA connectors Xilinx Personality Module XPM interface for access to RocketIO transceivers SPI4 2 GPIO Power JTAG and trace debug ports Encryption battery Fa...

Page 23: ...locations for additional documentation on Xilinx tools and solutions EDK www xilinx com edk ISE www xilinx com ise Answer Browser www xilinx com support Virtex 4 FPGAs www xilinx com virtex 4 Figure 2...

Page 24: ...U JTAG Header J12 Parallel Cable IV PC4 JTAG J9 Reset Switches SW1 SW2 PCI Slots 3 3V and 5 5V PCI Express Slots CompactFlash Slot J22 IDE Drive Connectors J15 J16 PM1 Expansion Slot MGT Differential...

Page 25: ...GA I O banks used by the ML410 platforms is summarized in Table 2 1 Digitally Controlled Impedance DCI Some FPGA banks can support the DCI feature in Virtex 4 FPGAs Support for DCI is summarized in Ta...

Page 26: ...quired a second user clock can be brought into the FPGA by installing a second oscillator in the X10 socket High precision clock signals can be supplied to the FPGA using differential clock signals br...

Page 27: ...IICLK_NQ0 DS90CP22 U6 MUX Q0 Q1 CLK250_Q0 CLK250_NQ0 MGT_SMA_CLK_P MGT_SMA_CLK_N 100 MHz LVDS CLK100_Q1 CLK100_NQ1 24 MHz 300 MHz X7 SATACLK_Q0 U47 ICS844031I 1 SATACLK_NQ0 100 MHz HCSL P53 P54 100 MH...

Page 28: ...LK_BOT PM2 F10 AD21 Personality module clock bottom 2 5V 1 LVDS_CLKEXT_P PM1 F12 J1 LVDS pair 2 5V 1 2 Frequency is user defined LVDS_CLKEXT_N PM1 F11 K1 LVDS pair 2 5V 1 2 Frequency is user defined S...

Page 29: ...ial pair that drives both DDR chips The delay on the clock trace is designed to match the delay of the other DDR control and data signals The DDR component clock is also fed back to the FPGA to allow...

Page 30: ...CAS_N 22 22 DDR1_DQS 0 F20 DDR1_DQS 0 16 DDR1_DQS 1 G20 DDR1_DQS 1 51 DDR1_DQS 2 G25 DDR1_DQS 2 16 DDR1_DQS 3 F25 DDR1_DQS 3 51 DDR1_DM 0 F21 DDR1_DM 0 20 DDR1_DM 1 G22 DDR1_DM 1 47 DDR1_DM 2 E23 DDR1...

Page 31: ...1_CS_N C27 DDR1_CS_N 24 24 DDR1_CKE H14 DDR1_CKE 44 44 DDR1_LOOP E26 DDR1_LOOP G17 DDR1_CK1_P F28 DDR1_CK1_P 45 45 DDR1_CK1_N E28 DDR1_CK1_N 46 46 DDR1_CLK_FB K18 DDR1_CLK_FB DDR1_BA 0 J25 DDR1_BA 0 2...

Page 32: ...with EDK supports registered DRR2 memory interfaces Please review the EDK Processor IP User Guide Ref 2 when migrating to a different DDR2 DIMM DDR2 Clock Signal The DDR2 clock signal is broadcast fr...

Page 33: ...ODT 195 DDR2_LOOP Bank 9 M26 DDR2_LOOP Bank 11 AB26 DDR2_DQSn 0 E29 DDR2_DQS 00 6 DDR2_DQS 0 F29 DDR2_DQS 00 7 DDR2_DQSn 1 J29 DDR2_DQSn 01 15 DDR2_DQS 1 K29 DDR2_DQS 01 16 DDR2_DQSn 2 P26 DDR2_DQSn 0...

Page 34: ...25 DDR2_DM 1 M31 DDR2_DQM 01 134 DDR2_DM 2 T30 DDR2_DQM 02 146 DDR2_DM 3 U28 DDR2_DQM 03 155 DDR2_DM 4 AJ32 DDR2_DQM 04 202 DDR2_DM 5 AG31 DDR2_DQM 05 211 DDR2_DM 6 AG30 DDR2_DQM 06 223 DDR2_DM 7 AF29...

Page 35: ..._DQ 25 C29 DDR2_DQ 25 34 DDR2_DQ 26 D29 DDR2_DQ 26 39 DDR2_DQ 27 J30 DDR2_DQ 27 40 DDR2_DQ 28 L29 DDR2_DQ 28 152 DDR2_DQ 29 N29 DDR2_DQ 29 153 DDR2_DQ 30 P29 DDR2_DQ 30 158 DDR2_DQ 31 R29 DDR2_DQ 31 1...

Page 36: ...Y26 DDR2_DQ 51 108 DDR2_DQ 52 AA30 DDR2_DQ 52 217 DDR2_DQ 53 AB30 DDR2_DQ 53 218 DDR2_DQ 54 AC30 DDR2_DQ 54 226 DDR2_DQ 55 AD30 DDR2_DQ 55 227 DDR2_DQ 56 AF30 DDR2_DQ 56 110 DDR2_DQ 57 V29 DDR2_DQ 57...

Page 37: ...d MDC controls and individual 25 MHz clock crystals Figure 2 5 DDR2 DIMM Block Diagram UG085_04_113005 IDELAYCTRL REFCLK PLB DDR2 SDRAM Core FPGA U37 DCM CLKIN PLB_Clk Device_Clk Device_Clk_n Device_C...

Page 38: ...on Settings for MII RGMII PHY Configuration Power On Settings 5 bit PHY address 1 0b00111 Interrupt polarity Active Low MDC MDIO interface Enabled Auto negotiate Slave operational at 10 100 1000 Mb s...

Page 39: ...the signals on each interface Figure 2 7 MII Interface Figure 2 8 RGMII Interface PHY_TXER PHY_TXCLK UG085_07_111505 PHY_TXCTL_TXEN PHY_TXD 3 0 PHY_RXER PHY_RXCLK PHY_RXCTL_RXDV PHY_RXD 3 0 PHY_RESET...

Page 40: ...1 K12 x x PHY_TXD0 K13 x x PHY_TXER L14 x Transmit controls PHY_TXCTL_TXEN 1 L11 x x PHY_RXD3 J9 x x Receive data bits PHY_RXD2 J10 x x PHY_RXD1 J11 x x PHY_RXD0 J12 x x PHY_RXER H18 x Receive control...

Page 41: ...w MDC MDIO interface Enabled Auto negotiate Slave operational at 10 100 1000 Mb s MDI crossover Enabled Fibre copper auto select Disabled Energy detect Disabled MAC pause Disabled Notes 1 PHY address...

Page 42: ...2 December 11 2008 Chapter 2 ML410 Embedded Development Platform R Figure 2 9 SGMII Interface PHY1_TXD_P UG085_09_111505 PHY1_TXD_N PHY1_RXD_P PHY1_RXD_N PHY1_MDC PHY1_MDIO FPGA SGMII Interface PHY U...

Page 43: ...120605 U7 From FPGA From FPGA Serial Port A Serial Port B VCC3V3 VCC3V3 MAX3232 DIN1 V C2 C1 RIN1 DOUT1 ROUT2 DOUT2 ROUT1 C1 RIN2 V DIN2 VCC GND C2 11 6 4 3 13 14 9 7 12 1 8 2 10 16 15 5 C327 0 1UF C3...

Page 44: ...a single CompactFlash card The configuration address switches allow the user to choose which of the eight configuration images to use System ACE error and status LEDs indicate the operational state of...

Page 45: ...gure 2 11 shows the connections between the JTAG connector System ACE CF controller and the FPGA The CPU JTAG header J12 is used to access the JTAG interface when J27 is jumpered See JTAG Source Selec...

Page 46: ...tFlash card as a file system The System ACE MPU interface is capable of supporting 16 bit or 8 bit modes of operation because all 16 data lines are wired to the FPGA Table 2 15 shows the connection be...

Page 47: ...5 44 SYSACE_MPA 6 AF3 SYSACE_MPA 06 43 SYSACE_MPD 0 AG6 SYSACE_MPD 00 66 SYSACE_MPD 1 AG5 SYSACE_MPD 01 65 SYSACE_MPD 2 AG3 SYSACE_MPD 02 63 SYSACE_MPD 3 AH5 SYSACE_MPD 03 62 SYSACE_MPD 4 AH4 SYSACE_M...

Page 48: ...23 24 Voltage Level Translator U35 LCD_DB7 LCD_DB6 LCD_DB5 LCD_DB4 LCD_DB3 LCD_DB2 LCD_DB1 LCD_DB0 FPGA_LCD_DB0 FPGA_LCD_DB4 FPGA_LCD_DB5 FPGA_LCD_DB6 FPGA_LCD_DB3 FPGA_LCD_DB2 FPGA_LCD_DB1 FPGA_LCD_...

Page 49: ...njunction with the eight LCD data signals defined in Table 2 17 See the AND491GST LCD display data sheet located on the ML410 documentation CD for more information Table 2 16 GPIO LED Connection from...

Page 50: ...elopment tools The JTAG port interface supports the attachment of external debug tools such as the ChipScope Integrated Logic Analyzer a tool providing logic analyzer capabilities for signals inside a...

Page 51: ...pin Mictor connector that combines the CPU Trace and the CPU Debug interfaces for high speed controlled impedance signaling For more information on starting and stopping the processor single stepping...

Page 52: ...TMS AM7 17 ATD_18 AH13 18 CPU_TDI AK29 19 ATD_17 AJ11 20 CPU_TRST_N AH27 21 ATD_16 AK7 22 ATD_15 AK21 23 TRC_TS1O AH7 24 ATD_14 AH24 25 TRC_TS2O AG10 26 ATD_13 AK11 27 TRC_TS1E AH8 28 ATD_12 AL21 29 T...

Page 53: ...o the PPC405 JTAG debug resources using normal FPGA routing resources The JTAG debug resources are not hard wired to particular pins and are available for attachment in the FPGA fabric making it possi...

Page 54: ...ctor does not support plug and play protocol via ID0 ID1 pins Table 2 21 Connections from FPGA to DAC Signal Name FPGA Pin U37 Description VGA_R0 F10 Red pixel data outputs VGA_R1 F11 VGA_R2 G10 VGA_R...

Page 55: ...Refer to Appendix A Board Revisions for a summary of features and devices available on each board The PCI Express interface supports MGTs operating at 2 5 Gb s Power is activated to the PCI Express sl...

Page 56: ...t Name FPGA Pin U37 Connector Pin P53 RXPPADA_103 R34 16 RXNPADA_103 T34 17 RXPPADB_103 AC34 21 RXNPADB_103 AD34 22 TXPPADA_103 V34 96 TXNPADA_103 W34 106 TXPPADB_103 Y34 101 TXNPADB_103 AA34 102 RXPP...

Page 57: ...lemented in the FPGA fabric The primary PCI bus is wired so that the FPGA fabric must be used to provide PCI bus arbitration logic EDK also provides PCI Arbiter IP See the EDK Processor IP User Guide...

Page 58: ...in card slots P5 and P3 Two 5V keyed PCI add in card slots P6 and P4 Figure 2 17 shows the connectivity of the PCI bus and PCI devices For more information on the PCI slot pinouts refer to the PCI Lo...

Page 59: ...LK5_FB H17 PCI_P_CLK5 PCI_INTA_N P5 PCI Interrupt Signals PCI_INTB_N R8 PCI_INTC_N P9 PCI_INTD_N V4 PCI_REQ0_N T3 PCI Request Signals PCI_REQ1_N R7 PCI_REQ2_N T8 PCI_REQ3_N T9 PCI_REQ4_N R9 PCI_GNT0_N...

Page 60: ...AD 10 F5 PCI_AD 11 G3 PCI_AD 12 L9 PCI_AD 13 L10 PCI_AD 14 J4 PCI_AD 15 J5 PCI_AD 16 H4 PCI_AD 17 H5 PCI_AD 18 N9 PCI_AD 19 N10 PCI_AD 20 K3 PCI_AD 21 K4 PCI_AD 22 J6 PCI_AD 23 J7 PCI_AD 24 M8 PCI_AD...

Page 61: ...MI U15 ALi IDE 0x5229 0x10B9 0 11 AD27 3 3 INT NMI U15 ALi Audio 0x5451 0x10B9 0 1 AD17 3 3 INT NMI U15 ALi Modem 0x5457 0x10B9 0 3 AD19 3 3 INT NMI U15 ALi USB 1 0x5237 0x10B9 0 15 AD31 3 3 INT NMI U...

Page 62: ...n CD for more information ALi M1535D supports the following features 1 parallel port 2 USB ports 2 IDE connectors GPIO SMBus interface AC 97 audio codec PS 2 keyboard and mouse Figure 2 18 ALi South B...

Page 63: ...is an implementation of the Universal Serial Bus Specification Version 1 0a see www usb org that contains two PCI Host Controllers and an integrated Root Hub The two USB connectors A B are part of the...

Page 64: ...tion USB_VCC 1 USB Power 5V MOSFET Isolated USB0_DN USB1_DN 2 USB Data USB0_DP USB1_DP 3 USB Data GND 4 Ground Table 2 29 ALi South Bridge IDE Connections IDE Primary Pin J16 Schematic Signal IDE Seco...

Page 65: ..._DMACK_N 29 SIDE_DMACK_N 30 GND 30 GND 31 PIDE_INTRQ 31 SIDE_INTRQ 32 NC 32 NC 33 PIDE_A1 33 SIDE_A1 34 PIDE_PDIAG_N 34 SIDE_PDIAG_N 35 PIDE_A0 35 SIDE_A0 36 PIDE_A2 36 SIDE_A2 37 PIDE_CS1_N 37 SIDE_C...

Page 66: ...s quick send byte receive byte write byte write word read word block read block write command with clock synchronization function and 10 bit addressing ability See IIC SMBus Interface page 69 for more...

Page 67: ...t and right CD ROM inputs a microphone input left and right channel line outputs and an amplified headphone output suitable for driving an 8 load using the LM4880 U2 The microphone input and right lef...

Page 68: ...f flash memory ML410 platforms provide connectivity to an AM29F040B 4 Mb 512 K x 8 bit flash memory U4 via the ALi M1535D ROM interface Table 2 34 shows the connections between the ALi M1535D U15 ROM...

Page 69: ...the rest of the system SMBus uses IIC as its backbone EDK provides IP that integrates the IIC interface with a microprocessor system See the EDK Processor IP User Guide Ref 2 for more details IIC SMBu...

Page 70: ...ock Figure 2 19 shows a block diagram of the FPGA in relation to the SMBus accelerator and the IIC bus Note Either the FPGA or the ALi M1535D can master the IIC bus but not simultaneously Table 2 35 I...

Page 71: ...tor LTC1694 ADDR 0x5C ADDR 0xA2 Real Time Clock ADDR 0xA0 EEPROM SPD EEPROM Voltage Temp Monitor Temperature U20 LM87 VCC12V_P VCC5V VCC2V5 VVCC3_PCI VCC1V2 Write Protect Jumper Off IIC Bus PCI Bus U2...

Page 72: ...put data from the master device that is shifted into a slave device Master In Slave Out MISO A data line that supplies the output data from a slave device that is shifted into the master device Serial...

Page 73: ...MGT on the FPGA A 300 MHz differential reference clock is provided for use with the SATA MGTs and logic used to support the SATA protocol For more information see the Virtex 4 RocketIO MGT User Guide...

Page 74: ...E CF controller U38 through the SYSTEMACE_RESET_N signal When the System ACE CF device is reset it causes the FPGA to be reconfigured The ACE file used to program the device is selected via SW3 DIP sw...

Page 75: ...tion address pins on the System ACE CF controller The addresses CFGADDR0 CFGADDR1 and CFGADDR2 are marked on SW3 as positions 1 2 and 3 respectively SW3 also has an ON indicator and directional arrow...

Page 76: ...Logic 0 To control the select lines from the FPGA switches 1 and 2 must be set to the open OFF position to prevent contention Switch position 3 is not used Table 2 39 shows the pinout for the select...

Page 77: ...J23 Eight System ACE configuration selections Connects to the three System ACE configuration address lines System ACE Reset Active Low input pulsed CPU Reset Active Low input pulsed The front panel i...

Page 78: ...ndicator tie this pin to anode of user s LED and cathode to ground 8 GND Ground 9 ATX_PWRLED ATX 3 3V power indicator tie this pin to anode of user s LED and cathode to ground 10 ATX_SPKR Used to driv...

Page 79: ...er on sequencing of the board JTAG Source Select J27 The JTAG source select jumper J27 enables the use of either the PC4 JTAG connector J9 or the CPU JTAG J12 and FPGA JTAG TRACE P8 to source the FPGA...

Page 80: ...section on the ML410 documentation CD The Sparkle power supply supports a full range input to automatically accommodate a wide range of voltage frequency standards such as 115V for North America Japa...

Page 81: ...3V3 VCC3_PCI 3V 500 mA U41 LT1763CS8 MGT_RTERM_105 1 25 25mA U10 REF2912 MGT_RTERM_110 1 25 25mA U25 REF2912 MGT_ACCAUXTX 1 1V 4A Q6 MAX8556 MGT_VTTRX 1 1V 4A Q7 MAX8556 MGT_ACCAUXRXB 1 1V 4A Q8 MAX85...

Page 82: ...e ML410 employs a SMBus device LM87 which samples several of the same supply voltages when accessed over the System Management Bus See the IIC SMBus Interface section for more information Figure 2 23...

Page 83: ...gulated FPGA board logic and DDR power VCC3_PCI 3 0V TP10 DS4 Regulated FPGA PCI bank 1 2 voltage VCC3V3 3 3V TP8 DS2 Regulated PCI and other logic VCC5V 5V TP16 DS7 From ATX power supply all regulato...

Page 84: ...platforms The PM connectors are Tyco Z Dok docking connectors See the 1367550 5 data sheet at Tyco s website www z dok com The ML410 is the host board functioning as the development platform for the V...

Page 85: ...45 Figure 2 25 Edge View of Host Board Connectors Figure 2 26 Host Board Connector Pin Detail PM1 Host Board Connector PM2 Host Board Connector UG085_24_111505 Plastic Divider Copper Pins D 2 D 2 D 1...

Page 86: ...at 2 5V can be used as 78 single ended I O at 2 5V 1 single ended clock at 2 5V 1 pin not connected Adapter Board PM Connectors Tyco Z Dok adapter board connectors part number 1367555 1 are the recep...

Page 87: ...re 2 27 Adapter Board Connector Pin Detail B 1 B 1 C 2 C 2 C 1 C 1 B 3 B 3 C 4 C 4 C 3 C 3 A 2 A 2 A 1 A 1 B 2 B 2 A 4 A 4 A 3 A 3 B 4 B 4 E 1 E 1 F 2 F 2 F 1 F 1 E 3 E 3 F 4 F 4 F 3 F 3 D 2 D 2 D 1 D...

Page 88: ...page 89 Contact Order The Z Dok power and ground pins contact in the following order 1 and 6 then 2 and 5 then 3 and 4 PM1 Power and Ground Table 2 47 shows the power and ground pins for the PM1 conn...

Page 89: ...O_L26N_12 PM_IO_3V_9 3V Single ended 50 impedance A10 AM3 IO_L26P_12 PM_IO_3V_13 3V Single ended 50 impedance A11 AK14 IO_L31P_8 PM_IO_82 2 5V LVDS pair 100 differential impedance can also be used as...

Page 90: ..._8 PM_IO_93 2 5V Single ended 50 impedance D3 AE14 IO_L13P_8 PM_IO_84 2 5V Single ended 50 impedance D4 AF14 IO_L13N_8 PM_IO_85 2 5V Single ended 50 impedance D5 Y7 IO_L5N_12 PM_IO_3V_21 3V Single end...

Page 91: ...dance F9 K16 IO_L2P_GC_VRN_LC_3 PM_CLK_TOP 2 5V Clock F10 NC NC NC NC No Connect F11 K1 MGTCLK_N_113 LVDS_CLKEXT_ N 2 5V LVDS pair 100 differential impedance can also be used as single ended F12 J1 MG...

Page 92: ...impedance can also be used as single ended A16 AE23 IO_L20N_VREF_7 PM_IO_23 2 5V A17 AM28 IO_L13N_7 PM_IO_32 2 5V LVDS pair 100 differential impedance can also be used as single ended A18 AM27 IO_L13P...

Page 93: ...lso be used as single ended A16 AE23 IO_L20N_VREF_7 PM_IO_23 2 5V A17 AM28 IO_L13N_7 PM_IO_32 2 5V LVDS pair 100 differential impedance can also be used as single ended A18 AM27 IO_L13P_7 PM_IO_33 2 5...

Page 94: ...impedance can also be used as single ended D4 AJ12 IO_L26P_8 PM_IO_68 2 5V D5 AL18 IO_L2N_7 PM_IO_59 2 5V LVDS pair 100 differential impedance can also be used as single ended D6 AL19 IO_L2P_7 PM_IO_...

Page 95: ...IO_L26P_SM6_7 PM_IO_36 2 5V F9 NC NC NC 2 5V No Connect F10 AD21 IO_L1P_GC_LC_4 PM_CLK_BOT 2 5V Clock F11 AL10 IO_L16P_8 PM_IO_6 2 5V LVDS pair 100 differential impedance can also be used as single e...

Page 96: ...96 www xilinx com ML410 Embedded Development Platform UG085 v1 7 2 December 11 2008 Chapter 2 ML410 Embedded Development Platform R Downloaded from Elcodis com electronic components distributor...

Page 97: ...Top RJ 45 SGMII Bottom RJ 45 PHY address 0b00111 MII RGMII Top RJ 45 SGMII Bottom RJ 45 PHY address 0b00111 MII RGMII Top RJ 45 SGMII Bottom RJ 45 SGMII MGT Clock 3 125 MHz 250 MHz 250 MHz SATA MGT Cl...

Page 98: ..._NQ0 DS90CP22 U6 MUX Q0 Q1 CLK125_Q0 CLK125_NQ0 MGT_SMA_CLK_P MGT_SMA_CLK_N 25 MHz 150 MHz X7 SATACLK_Q0 U47 ICS844001 1 SATACLK_NQ0 100 MHz P53 P54 100 MHz OSC in Socket Empty Socket 33 MHz PCIE_SLOT...

Page 99: ...e through SW6 SGMIICLK_NQ0 Fixed N34 SMA or onboard 125 MHz clock source selectable through SW6 MGTCLK_P_110 Fixed AP3 SMA or onboard 125 MHz clock source selectable through SW6 MGTCLK_N_110 Fixed AP4...

Page 100: ...100 www xilinx com ML410 Embedded Development Platform UG085 v1 7 2 December 11 2008 R Downloaded from Elcodis com electronic components distributor...

Page 101: ...ce Guide 2 Processor IP User Guide www xilinx com ise embedded proc_ip_ref_guide pdf 3 DS302 Virtex 4 Data Sheet 4 UG076 Virtex 4 RocketIO Transceiver User Guide 5 DS080 System ACE CompactFlash Soluti...

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