Xilinx ML410, User Manual

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28 www.xilinx.com ML410 Embedded Development Platform
UG085 (v1.7.2) December 11, 2008
Chapter 2: ML410 Embedded Development Platform
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Table 2-3 shows the ML410 clock connections.
Table 2-3: Clock Connections
Schematic Net Name
Clock
Source
FPGA Pin (U37) Description
USER_CLKSYS X6 J16 100 MHz socketed user clock
oscillator (2.5V).
USER_CLK2 X10 L15 Socket for user-supplied clock
oscillator (3.3V)
(1)
.
USER_SMA_CLK_N J36 AG18 100
Ω
differential SMA
connections that can be used as a
differential pair clock.
USER_SMA_CLK_P J17 AF18 100
Ω
differential SMA
connections that can be used as a
differential pair clock. J17 can be
used single ended at 50
Ω
.
PM_CLK_TOP PM1.F9 K16 Personality module clock (top)
(2.5V)
(1)
.
PM_CLK_BOT PM2.F10 AD21 Personality module clock
(bottom) (2.5V)
(1)
.
LVDS_CLKEXT_P PM1.F12 J1 LVDS pair (2.5V)
(1) (2)
.
Frequency is user-defined.
LVDS_CLKEXT_N PM1.F11 K1 LVDS pair (2.5V)
(1) (2)
.
Frequency is user-defined.
SGMIICLK_Q0 (Selectable) M34
SMA or onboard 250 MHz clock
source selectable through
SW6
(2)
.
SGMIICLK_NQ0 (Selectable) N34
SMA or onboard 250 MHz clock
source selectable through
SW6
(2)
.
MGTCLK_P_110 (Selectable) AP3
SMA or onboard 250 MHz clock
source selectable through
SW6
(2)
.
MGTCLK_N_110 (Selectable) AP4
SMA or onboard 250 MHz clock
source selectable through
SW6
(2)
.
SATACLK_Q0 (Selectable) AP29 300 MHz Serial ATA clock
(2)
.
SATACLK_NQ0 (Selectable) AP28 300 MHz Serial ATA clock
(2)
.
Notes:
1. See “High-Speed I/O,” page 84 .
2. These clocks are differential pairs through the RocketIO transceivers and are not available on ML410-P
boards. See Figure 2-3, page 27 .
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