Xilinx MicroBlaze, Reference Manual

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MicroBlaze Processor Reference Guide www.xilinx.com 135
UG081 (v14.7)
Debug Interface Description
Debug Interface Description
The debug interface on MicroBlaze is designed to work with the Xilinx Microprocessor Debug
Module (MDM) IP core. The MDM is controlled by the Xilinx Microprocessor Debugger (XMD)
through the JTAG port of the FPGA. The MDM can control multiple MicroBlaze processors at the
same time. The debug signals are grouped in the DEBUG bus. The debug signals on MicroBlaze are
listed in
Table 3-15 .
Trace Interface Description
The MicroBlaze core exports a number of internal signals for trace purposes. This signal interface is
not standardized and new revisions of the processor may not be backward compatible for signal
selection or functionality. It is recommended that you not design custom logic for these signals, but
rather to use them via Xilinx provided analysis IP. The trace signals are grouped in the TRACE bus.
The current set of trace signals were last updated for MicroBlaze v7.30 and are listed in
Table 3-16 .
The Trace exception types are listed in Table 3-17 . All unused Trace exception types are reserved.
Table 3-15: MicroBlaze Debug Signals
Signal Name Description VHDL Type Direction
Dbg_Clk
JTAG clock from MDM std_logic input
Dbg_TDI
JTAG TDI from MDM std_logic input
Dbg_TDO
JTAG TDO to MDM std_logic output
Dbg_Reg_En
Debug register enable from
MDM std_logic input
Dbg_Shift
1
1. Updated for MicroBlaze v7.00: Dbg_Shift added and Debug_Rst included in DEBUG bus
JTAG BSCAN shift signal from
MDM std_logic input
Dbg_Capture
JTAG BSCAN capture signal
from MDM std_logic input
Dbg_Update
JTAG BSCAN update signal
from MDM std_logic input
Debug_Rst
1
Reset signal from MDM, active
high. Should be held for at least
1
Clk
clock cycle.
std_logic input
Table 3-16: MicroBlaze Trace Signals
Signal Name Description VHDL Type Direction
Trace_Valid_Instr
Valid instruction on trace port. std_logic output
Trace_Instruction
1
Instruction code std_logic_vector (0 to 31) output
Trace_PC
1
Program counter std_logic_vector (0 to 31) output
Trace_Reg_Write
1
Instruction writes to the register file std_logic output
Trace_Reg_Addr
1
Destination register address std_logic_vector (0 to 4) output
Trace_MSR_Reg
1
Machine status register std_logic_vector (0 to 14)
2
output
Trace_PID_Reg
1,2
Process identifier register std_logic_vector (0 to 7) output
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