Xilinx MicroBlaze, Reference Manual

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136 www.xilinx.com MicroBlaze Processor Reference Guide
UG081 (v14.7)
Chapter 3: MicroBlaze Signal Interface Description
Trace_New_Reg_Value
1
Destination register update value std_logic_vector (0 to 31) output
Trace_Exception_Taken
1
Instruction result in taken exception std_logic output
Trace_Exception_Kind
1,3
Exception type. The description for the
exception type is documented below. std_logic_vector (0 to 4)
2
output
Trace_Jump_Taken
1
Branch instruction evaluated true, i.e taken std_logic output
Trace_Jump_Hit
1,4,6
Branch Target Cache hit std_logic output
Trace_Delay_Slot
1
Instruction is in delay slot of a taken branch std_logic output
Trace_Data_Access
1
Valid D-side memory access std_logic output
Trace_Data_Address
1
Address for D-side memory access std_logic_vector (0 to 31) output
Trace_Data_Write_Value
1
Value for D-side memory write access std_logic_vector (0 to 31) output
Trace_Data_Byte_Enable
1
Byte enables for D-side memory access std_logic_vector (0 to 3) output
Trace_Data_Read
1
D-side memory access is a read std_logic output
Trace_Data_Write
1
D-side memory access is a write std_logic output
Trace_DCache_Req
Data memory address is within D-Cache
range std_logic output
Trace_DCache_Hit
Data memory address is present in D-Cache std_logic output
Trace_DCache_Rdy
Data memory address is within D-Cache
range and the access is completed std_logic output
Trace_DCache_Read
5
The D-Cache request is a read std_logic output
Trace_ICache_Req
Instruction memory address is within
I-Cache range
std_logic output
Trace_ICache_Hit
Instruction memory address is present in
I-Cache
std_logic output
Trace_ICache_Rdy
Instruction memory address is within
I-Cache range and the access is completed
std_logic output
Trace_OF_PipeRun
Pipeline advance for Decode stage std_logic output
Trace_EX_PipeRun
6
Pipeline advance for Execution stage std_logic output
Trace_MEM_PipeRun
6
Pipeline advance for Memory stage std_logic output
Trace_MB_Halted
2
Pipeline is halted by debug std_logic output
1. Valid only when Trace_Valid_Instr = 1
2. Updated for MicroBlaze v7.00: 4 bits added to Trace_MSR_Reg, Trace_PID_Reg added, Trace_MB_Halted added, and 1 bit added to
Trace_Exception Kind
3. Valid only when Trace_Exception_Taken = 1
4. Updated for MicroBlaze v7.30: Trace_DCache_Rdy, Trace_DCache_Read, Trace_ICache_Rdy, and Trace_Jump_Hit added
5. Valid only when Trace_DCache_Req = 1
6. Not used with area optimization feature
Table 3-16: MicroBlaze Trace Signals (Continued)
Signal Name Description VHDL Type Direction
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