PLB PCI Full Bridge (v1.00a)
DS508 March 21, 2006
www.xilinx.com
49
Product Specification
EAR
LY
ACCESS
to the Configuration Data Port register initiates a Configuration Write transaction on the PCI bus.
Determination of whether the read or write transfer is type 0 or type 1 is done automatically.
Both type 0 and type 1 configuration transactions are supported. The type of transaction is determined
from the Bus number in the Configuration Address Port register (Bits 8-15) and the bus numbers in the
Bus Number/Subordinate Bus Number register. The local bus number is located at bits 8-15 and the
maximum subordinate bus number is located at bits 24-31 in the Bus Number/Subordinate Bus
Number register. If the Bus number in the Configuration Address Port register is equal to the local bus
number in the Bus Number/Subordinate Bus Number register (bits 8-15), a type 0 transaction is
performed. If the Bus number in the Configuration Address Port register is greater than the bus
number in the Bus Number/Subordinate Bus Number register and less than or equal to the maximum
subordinate Bus number, a type 1 transaction is performed. If a configuration transaction to a Bus
Number not satisfying the inequality relation is attempted, then PLB Sl_MErr is asserted. When a
configuration read from a bus number not in the subordinate bus range is initiated, nothing occurs on
the PCI bus and an IPIF timout occurs with the IPIF asserting PLB Sl_MErr. When a configuration write
to a bus number not in the subordinate bus range is initiated, nothing occurs on the PCI bus, the data
is discarded and PLB Sl_MErr is asserted. These conditions are equivalent to the situation where the
master enable bit in the configuration command register of the v3.0 core is not set.
If a configuration read to a device number not assigned to a device on the PCI bus is attempted, a
Master Abort occurs on the PCI bus, and all ones are returned on the PLB bus.
IDSEL is asserted for the device to be configured in all type 0 configuration transactions. The most
common implementation method for IDSEL is used in this bridge implementation where address lines
AD[31:16] are required to be mapped to IDSEL for each device.
The mapping is shown below.
• IDSEL of device 0 is connected to AD16
• IDSEL of device 1 is connected to AD17
• IDSEL of device 2 is connected to AD18.
• ...
• IDSEL of device 15 is connected to AD31
A decode of the device number in the Configuration Address Port is used to determine which address
line/IDSEL is asserted.
As noted, when the bridge has host bridge configuration functionality, IDSEL of the v3.0 core is
connected internally to the AD-bit specified by the C_BRIDGE_IDSEL_ADDR_BIT parameter.
C_NUM_IDSEL specifies the number of PCI agents that can be configured on the PCI bus by specifying
the number of IDSEL lines that are decoded and assigned to address lines AD[31:16]. Each device on
the bus must have its IDSEL line properly connected to the PCI AD bus. It can be resistively-coupled to
the associated address bit or direct coupling, if it is not detrimental to performance per PCI 2.2
specification. Because the v3.0 core does not support address stepping, resistive coupling of IDSEL
with the assigned address bit must be sufficient to ensure proper signal levels at IDSEL without
utilizing address stepping.
Multiple PLB PCI bridges can be instantiated on a given PLB. Each bridge has a unique base address
with fixed offset to corresponding unique set of configuration registers. The unique set of configuration
registers are used to perform configuration accesses on the unique primary PCI bus and its’
