PLB PCI Full Bridge (v1.00a)
DS508 March 21, 2006
www.xilinx.com
25
Product Specification
EAR
LY
ACCESS
Global Interrupt Enable Register Description
A global enable is provided to globally enable or disable interrupts from the PCI device. This bit is
AND’d with the output to the interrupt controller. Bit assignment is shown in
Table 7
. Unlike most
other registers, this bit is the MSB on the PLB. This bit is read/write and cleared upon reset.
Table 7:
Global Interrupt Enable Register Bit Definitions (Bit assignment assumes 32-bit bus)
Bit(s)
Name
Access
Reset
Value
Description
0
Interrupt Global
Enable
Read/Write
0x0
Interrupt Global Enable-
PLB bit (0) is the Interrupt
Global Enable bit. Enables all individually enabled
interrupts to be passed to the interrupt controller.
•
0 - Not enabled
•
1 - Enabled
1-31
Read
0x0
Unassigned-
Bridge Interrupt Register Description
The PLB PCI Bridge has twelve interrupt conditions. The Bridge Interrupt Enable Register enables each
interrupt independently. Bit assignment in the Interrupt register for a 32-bit data bus is shown in
Table 8
. The interrupt register is read-only and bits are toggled by writing a 1 to the bit(s) being cleared.
All bits are cleared upon reset. For more information, see the PLB IPIF Interrupt Product Specification;
the module is labeled PLB Interrupt module, but is used in the PLB IPIF.
Table 8:
Bridge Interrupt Register Bit Definitions (Bit Assignment Assumes 32-bit Bus)
Bit(s)
Name
Access
Reset
Value
Description
0-18
Read
0x0
Unassigned
19
PCI Initiator
Write SERR
Read/Write
1 to clear
0x0
PCI Initiator Write SERR-
Interrupt(19) indicates a SERR
error was detected during a PCI initiator write of data to a
PLB slave.
20
PCI Initiator
Read SERR
Read/Write
1 to clear
0x0
PCI Initiator Read SERR-
Interrupt(20) indicates a SERR
error was detected during a PCI initiator read of data from a
PLB slave.
21
Reserved
0x0
Reserved
22
PLB Master
Write Retry
Timeout
Read/Write
1 to clear
0x0
PLB Master Burst Write Retry Timeout-
Interrupt(22)
indicates the automatic PCI write retries were not
successful due to a latency timeout on the last retry during
a PLB Master burst write to a PCI target.
23
PLB Master
Write Retry
Disconnect
Read/Write
1 to clear
0x0
PLB Master Burst Write Retry Disconnect-
Interrupt(23)
indicates the automatic PCI write retries were not
successful due to a target disconnect on the last retry during
a PLB Master burst write to a PCI target.
24
PLB Master
Write Retry
Read/Write
1 to clear
0x0
PLB Master Write Retry-
Interrupt(24) indicates the
automatic PCI write retries were not successful due to a PCI
retry on the last retry during a PLB Master burst write to a
PCI target.
