Xilinx LogiCore PLB PCI Full Bridge Specification Download Page 13

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PLB PCI Full Bridge (v1.00a)

DS508 March 21, 2006

www.xilinx.com

Product Specification

EAR

ACCESS

G61

Include configuration
functionality via IPIF
transactions

C_INCLUDE_

PCI_CONFIG

0 = Not included
1 = Included

integer

G62

Number of IDSEL
signals supported

C_NUM_

IDSEL

1 to 16

integer

G63

PCI address bit that PCI
v3.0 core IDSEL is
connected to

C_BRIDGE_

IDSEL_ADDR_
BIT

31 down to 16
Must be <= 15 +
C_NUM_IDSEL.
AD(31 down to 0) index
labeling

integer

IPIF Parameters Group

G64

PLB master ID bus
width (set automatically
by XPS)

C_PLB_MID_

WIDTH

log

(C_PLB_NUM_MA

STERS)

integer

G65

Number of masters on
PLB bus (set
automatically by XPS)

C_PLB_NUM_

MASTERS

1-16

integer

G66

PLB Address width

C_PLB_

AWIDTH

32 (only allowed value

integer

G67

PLB Data width

C_PLB_

DWIDTH

64 (only allowed value

integer

G68

Specifies the target
technology

C_FAMILY

See PLB IPIF data
sheet

virtex2

string

Notes:

1. The range specified must comprise a complete, contiguous power of two range, such that the range = 2

and

the n least significant bits of the Base Address are zero.

2. The minimum address range specified by C_BASEADDR and C_HIGHADDR must be at least 0x1FF.

C_BASEADDR must be a multiple of the range, where the range is C_HIGHADDR - C_BA 1.

Table 1:

PLB PCI Bridge Interface Design Parameters

(Contd)

Generic

Feature /

Description

Parameter

Name

Allowable Values

Default

Value

VHDL

Type

Summary of Contents for LogiCore PLB PCI Full Bridge

Page 1: ...ribed in the 64 Bit Processor Local Bus Architecture Specification v3 5 Details on the Xilinx PLB and the PLB IPIF are found in the Processor IP Reference Guide This guide is accessed via EDK help or...

Page 2: ...t be used to access memory on the PLB side Configuration read and writes are supported including self configuration transactions only when upper word address lines are utilized for IDSEL lines The Con...

Page 3: ...er Completes posted write operations prior to initiating new operations Signal set required for integrating a PCI bus arbiter in the FPGA with the PLB PCI bridge is available at the top level of the P...

Page 4: ...cal Bus Intellectual Property InterFace It interfaces to the PLB bus The IPIF v3 0 Bridge It interfaces between the PLB IPIF and the v3 0 core The LogiCORE PCI32 Interface v3 0 core It interfaces to t...

Page 5: ...or Only PCI memory space is supported Address translations in both directions are performed as follows High order address bits are substituted for the address vector before crossing to the other bus d...

Page 6: ...igh order bit sub Addr to PCI IPIFBAR_2 PCIBAR_2 ds508_02_112205 Example 1 Because address translations are performed only when the PLB PCI Bridge is configured with FIFOs the example shown in Figure...

Page 7: ...ds 0x56710ABC on the PCI bus Accessing the PLB PCI Bridge IPIFBAR_1 with address 0xABCDF123 on the PLB bus yields 0xFEDC1123 on the PCI bus Accessing the PLB PCI Bridge IPIFBAR_2 with address 0xFFFEDC...

Page 8: ...or G4 PCI BAR to which IPIF BAR 0 is mapped unless C_INCLUDE_BAROFF SET_REG 1 C_IPIFBAR2 PCIBAR_0 1 Vector of length C_PLB_AWIDTH 0xFFFFFFFF std_logic_ vector G5 IPIF BAR 0 memory designator C_IPIF_SP...

Page 9: ...F BAR 4 is mapped unless C_INCLUDE_BAROFF SET_REG 1 C_IPIFBAR2 PCIBAR_4 Vector of length C_PLB_AWIDTH 0xFFFFFFFF std_logic_ vector G21 IPIF BAR 4 memory designator C_IPIF_SPACE TYPE_4 0 I O space 1 Me...

Page 10: ...ta bus width C_PCI_DBUS_ WIDTH 32 32 integer G35 Both PCI2IPIF FIFO address bus widths Usable depth is 2 C_PCI2IPIF_FIFO_A BUS_WIDTH 3 C_PCI2IPIF_ FIFO_ABUS_ WIDTH 4 14 9 integer G36 Both IPIF2PCI FIF...

Page 11: ...CI FIFO DEPTH 3 IPIF2PCI FIFO DEPH given by 2 C_IPIF2PCI_FIFO_ ABUS_WIDTH 16 integer G43 Number of PCI retry attempts in IPIF posted write operations C_NUM_PCI_R ETRIES_IN_ WRITES Any integer 3 intege...

Page 12: ...PCI Configuration Space Header Device ID C_DEVICE_ID 16 bit vector 0x0000 std_logic_ vector G54 PCI Configuration Space Header Vendor ID C_VENDOR_ ID 16 bit vector 0x0000 std_logic_ vector G55 PCI Con...

Page 13: ...Number of masters on PLB bus set automatically by XPS C_PLB_NUM_ MASTERS 1 16 8 integer G66 PLB Address width C_PLB_ AWIDTH 32 only allowed value 32 integer G67 PLB Data width C_PLB_ DWIDTH 64 only a...

Page 14: ...t PLB Bus I PLB main bus reset See table note 1 P4 PLB_ABus 0 C_PLB_ AWIDTH 1 PLB Bus I Note 1 applies from P4 to P53 P5 PLB_PAValid PLB Bus I P6 PLB_masterID 0 C_PLB _MID_WIDTH 1 PLB Bus I P7 PLB_abo...

Page 15: ...LB_MRdDAck PLB Bus I P39 PLB_MRdBTerm PLB Bus I P40 PLB_MWrBTerm PLB Bus I P41 M_request PLB Bus O P42 M_priority PLB Bus O P43 M_buslock PLB Bus O P44 M_RNW PLB Bus O P45 M_BE 0 C_PLB_DWIDT H 8 1 PLB...

Page 16: ...nals P63 INTR_A PCI Bus O Indicates that LogiCORE PCI interface requests an interrupt PCI Error Signals P64 PERR_N PCI Bus I O Indicates that a parity error was detected while the LogiCORE PCI interfa...

Page 17: ...n INTR_A behavior relative to v3 0 input INTR_N The v3 0 core command register interrupt disable bit controls the INTR_A operation and v3 0 core status register Interrupt status bit flags if v3 0 core...

Page 18: ...B memory space that is responded to by this device IPIF BAR G4 C_IPIFBAR2PCIBAR_0 G2 G3 and G48 Meaningful only if G48 0 and in this case only high order bits that are the same in G2 and G3 are meanin...

Page 19: ...4 then G18 to G19 define the range in PLB memory space that is responded to by this device IPIF BAR G19 C_IPIFBAR_HIGHADDR_4 G18 G1 and G18 Meaningful only if G1 4 then G18 to G19 define the range in...

Page 20: ...gful if G26 1 2 G33 C_PCI_ABUS_WIDTH Only 1 setting G34 C_PCI_DBUS_WIDTH Only 1 setting G35 C_PCI2IPIF_FIFO_ABUS_ WIDTH G36 C_IPIF2PCI_FIFO_ABUS_ WIDTH G37 C_INCLUDE_INTR_A_ BUF P63 If G37 0 an io buf...

Page 21: ...E_DEVNUM_ REG G63 G61 G62 If G61 0 G49 has no meaning If G49 and G61 1 G63 has no meaning Meaningful bits in the Device Number register are defined by G62 G50 C_NUM_IDELAYCTRL G68 If G68 Virtex 4 G50...

Page 22: ...as no meaning If G61 1 and G49 0 G63 must be consistent with the setting of G62 IPIF Parameters Group G64 C_PLB_MID_WIDTH G65 C_PLB_NUM_MASTERS G66 C_PLB_AWIDTH G67 C_PLB_DWIDTH G68 C_FAMILY G50 52 If...

Page 23: ...EADDR 0x04 Read Write Device Interrupt Enable Register IER C_BASEADDR 0x08 Read Write Device Interrupt ID IID C_BASEADDR 0x18 Read Global Interrupt Enable Register GIE C_BASEADDR 0x1C Read Write Bridg...

Page 24: ...ation Data Port Present only if G61 1 Bus Number Subordinate Bus Number Present only if G61 1 IPIFBAR2PCIBAR_0 High Order Bits Present only if G48 1 IPIFBAR2PCIBAR_1 High Order Bits Present only if G1...

Page 25: ...e the PLB IPIF Interrupt Product Specification the module is labeled PLB Interrupt module but is used in the PLB IPIF Table 8 Bridge Interrupt Register Bit Definitions Bit Assignment Assumes 32 bit Bu...

Page 26: ...clear 0x0 PLB Master Read Target Abort Interrupt 29 indicates that a target abort was detected by the v3 0 core when performing as a PCI initiator reading data from a PCI target 30 PLB Master Read PER...

Page 27: ...0 Not enabled 1 Enabled 26 PLB Master Write Target Abort Read Write 0x0 PLB Master Write Target Abort Enable Enables this interrupt to be passed to the interrupt controller 0 Not enabled 1 Enabled 27...

Page 28: ...Bus 1 256 24 D24 Read Write 0x0 Active high enable bit 25 31 D25 D31 Read 0x0 Reserved and hardwired to 0 Configuration Data Port Register Description The Configuration Data Port Register exists only...

Page 29: ...he low order bits hard wired to zero The IPIFBAR2PCIBAR_N registers are included in the bridge via the parameter C_INCLUDE_BAROFFSET_REG These read write registers allow dynamic run time changes of th...

Page 30: ...e translation to PCI memory and IO space For the previous example the following registers are set Register for C_IPIFBAR_0 IPIFBAR2PCIBAR_0 High Order Bit Register Programmable register for 16 high or...

Page 31: ...Device Number register is included by setting C_INCLUDE_DEVNUM_REG 1 The register can be included only if configuration functionality is included i e C_INCLUDE_PCI_CONFIG 1 This register is read writ...

Page 32: ...en the IPIF is operating as a PLB slave it performs single transfers of 1 8 bytes burst transfers of any number of double words and 4 8 or 16 word line transactions The IPIF always performs line read...

Page 33: ...t Supported Write Burst transfer double word I O Write Memory Write multiple data phase Not Supported Sequential fill 4 8 and 16 word cacheline write 2 I O Write Memory Write multiple data phase Not S...

Page 34: ...r insertion of wait states prior to the first data transfer Consequently if the PLB device requires throttling that affects the PCI transaction the PLB PCI Bridge must terminate the transaction If the...

Page 35: ...LB transaction will be terminated When the PLB master terminates the transaction with data remaining in the FIFO the FIFO is flushed Because the data is required to be prefetchable data is not lost wh...

Page 36: ...PCI transaction is attempted as long as the PLB master request is active If a retry is issued on a subsequent PCI transfer and the PLB master is requesting more data an automatic retry is issued when...

Page 37: ...d The bridge inhibits IPIF timeout while trying to get the requested data Target disconnect with data Completes PERR Data is transferred and the PLB Master Read PERR interrupt asserted Data transfer t...

Page 38: ...s the actual depth minus 3 words Data is loaded in the FIFO on each clock cycle that the write request is asserted and the address decode is valid If the transaction is not a burst i e PLB_wrBurst is...

Page 39: ...ite Retry interrupts Consistent with the PCI Spec the PLB master is required to perform the write again if the last of the automatic retries was terminated with a PCI retry If on a single transfer the...

Page 40: ...I target the bridge is available for a new write transaction Table 18 summarizes the abnormal conditions that a PCI target can respond with and how the response is translated to the PLB master Table 1...

Page 41: ...he PLB is double word aligned Every memory read multiple command that translates to a burst read operation is performed with the full 64 bits on the PLB independent of the byte enable specified by the...

Page 42: ...B PCI Bridge must disconnect with data because the v3 0 core does not allow throttling after the first data phase Throttling by the PLB slave and the v3 0 restriction of not allowing throttling of dat...

Page 43: ...a read multiple command is performed and a PLB rearbitrate is asserted by the PLB slave on the first request for data the PLB PCI Bridge commands the v3 0 core to disconnect without data i e PCI retry...

Page 44: ...st be memory space in the PCI sense the memory write command is the only write command from a remote PCI initiator to which the PLB PCI Bridge will respond The command decode and number words written...

Page 45: ...ter abort will occur see v3 0 core documentation If enabled the v3 0 core asserts SERR_N when address phase parity errors are detected If SERR_N is asserted by a remote agent in a data phase the bridg...

Page 46: ...s near the end of the valid range Table 20 summarizes most abnormal conditions that a PLB slave can respond with to a memory write command and how the response is translated to the PCI initiator Table...

Page 47: ...ctionality in the Command Status Register and sets the latency timer to maximum count for most any data value written to the registers This behavior is an artifact of the v3 0 core behavior Configurat...

Page 48: ...able 22 show examples only and do not show all the possible bit patterns Note that the bytes are swapped for maintaining byte addressing integrity The v3 0 core is PCI 2 2 compliant core but it has PC...

Page 49: ...e configuration command register of the v3 0 core is not set If a configuration read to a device number not assigned to a device on the PCI bus is attempted a Master Abort occurs on the PCI bus and al...

Page 50: ...ically retried until the transfer completes Automatically retried a parameterized number of times If the last of the PCI write command retries fail due to a PCI retry the PLB Master Burst Write Retry...

Page 51: ...is listed in Table 24 Table 24 PCI Bus Monitoring Signals Bit Index Signal Name Instantiated IO Buffer PCI Transaction Control Signals 0 FRAME_N Yes 1 DEVSEL_N Yes 2 TRDY_N Yes 3 IRDY_N Yes 4 STOP_N Y...

Page 52: ...design data sheet for details Additional bridge specific constraints are required and an example ucf file is provided in the EDK pcores library To remind the user that the additional bridge related co...

Page 53: ...EDK flow checks if the PCI clock is a PAD input and if it is then the OFFSET constraints shown below are includes in the bridge ngc file Time Specs Important Note The timespecs used in this section c...

Page 54: ...m the MHS file This allows upgrading to v1 02 a from v1 01 a without changing ports Recall that v1 01 a does not support the Virtex 4 architecture It is required that the 200 MHz clock be stable when...

Page 55: ...provided The FPGA Editor tool can be helpful to determine IDELAYCTRL LOC coordinates for the user s pinout The syntax for the ucf file LOC constraints is shown in the example below where the instance...

Page 56: ...can change in with future versions of the tools Virtex 4 Only Constraints INST XPCI_CBD IOBDELAY_TYPE VARIABLE INST XPCI_ADD IOBDELAY_TYPE VARIABLE INST PCI_CORE XPCI_PARD IOBDELAY_TYPE VARIABLE INST...

Page 57: ...reated that instantiated the PLB PCI bridge with the parameters set as outlined in Table 25 The data is shown for a Virtex II Pro device for Virtex 4 devices and an additional GCLK is required for the...

Page 58: ...important to understanding the PLB PCI Bridge design Processor IP Reference Guide Xilinx LogiCORE PCI Interface v3 0 Product Specification Xilinx The Real PCI Design Guide v3 0 IPSPECXXX PLB IPIF Log...

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