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1-Gigabit Ethernet MAC v8.5 User Guide

UG144 April 24, 2009

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Chapter 7: Using the Physical Side Interface

Figure 7-1:

External GMII Transmitter Logic

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Figure 7-2:

External GMII Receiver Logic for Spartan-3, Spartan-3E, and

Spartan-3A Devices

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Figure 7-3:

External GMII Receiver Logic for Virtex-5 Devices

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Figure 7-4:

External RGMII Transmitter Logic

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Figure 7-5:

External RGMII Transmitter Logic in Virtex-4 Devices

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Figure 7-6:

External RGMII Transmitter Logic in Virtex-5 Devices

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Figure 7-7:

External RGMII Receiver Logic

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Figure 7-8:

External RGMII Receiver Logic for Virtex-4 Devices

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Figure 7-9:

External RGMII Receiver Logic for Virtex-5 Devices

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Figure 7-10:

RGMII Inband Status Decoding Logic

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Figure 7-11:

Creating an External MDIO Interface

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Chapter 8: Configuration and Status

Figure 8-1:

Configuration Register Write Timing

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Figure 8-2:

Configuration Register Read Timing

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Figure 8-3:

Address Table Write Timing

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Figure 8-4:

Address Table Read Timing

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Figure 8-5:

Typical MDIO-managed System

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Figure 8-6:

MDIO Write Transaction

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Figure 8-7:

MDIO Read Transaction

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Figure 8-8:

MDIO Access through Management Interface

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Chapter 9: Constraining the Core

Figure 9-1:

Input GMII Timing

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Figure 9-2:

Timing Report Setup/Hold Illustration

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Figure 9-3:

Input RGMII Timing

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Figure 9-4:

Timing Report Setup/Hold Illustration

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Chapter 10: Clocking and Resetting

Figure 10-1:

Clock Management Logic with External GMII

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Figure 10-2:

Clock Management with External RGMII

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Figure 10-3:

Clock Management Logic with External GMII (Multiple Cores)

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Figure 10-4:

Clock Management Logic with External RGMII (Multiple Cores)

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Figure 10-5:

Reset Circuit for a Single Clock/reset Domain

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Summary of Contents for LogiCORE IP MAC v8.5

Page 1: ...R DISCONTINUED PRODUCT LogiCORE IP 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009...

Page 2: ...BASED THEREON INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF INFRINGEMENT AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A...

Page 3: ...ion 7 0 Xilinx tools v8 1i 07 13 06 4 0 Updated to 1 Gigabit Ethernet MAC version 8 0 Xilinx tools v8 2i 09 21 06 4 1 Updated to 1 Gigabit Ethernet MAC version 8 1 added support for Spartan 3A platfor...

Page 4: ...www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT...

Page 5: ...hnical Support 20 Feedback 20 GEMAC Core 20 Document 20 Chapter 2 Core Architecture System Overview 21 Core Components 22 Core Interfaces 23 GMAC Core with Optional Management Interface 23 GMAC Core W...

Page 6: ...er 44 Receiver Statistics Vector 44 Transmitting Outbound Frames 47 Normal Frame Transmission 47 Padding 47 Client Supplied FCS Passing 48 Client Underrun 48 VLAN Tagged Frames 49 Maximum Permitted Fr...

Page 7: ...when Implementing an External GMII 96 Understanding Timing Reports for GMII Setup Hold Timing 99 Constraints when Implementing an External RGMII 101 Understanding Timing Reports for RGMII Setup Hold t...

Page 8: ...ation Model 125 Using the Model 126 Other Implementation Information 126 Appendix A Using the Client Side FIFO Interfaces 128 Transmit FIFO 128 Receive FIFO 129 Overview of LocalLink Interface 130 Dat...

Page 9: ...e Example Design 36 Chapter 5 Using the Client Side Data Path Figure 5 1 Normal Frame Reception 40 Figure 5 2 Frame Reception with Error 41 Figure 5 3 Frame Reception with In Band FCS Field 42 Figure...

Page 10: ...n External MDIO Interface 76 Chapter 8 Configuration and Status Figure 8 1 Configuration Register Write Timing 84 Figure 8 2 Configuration Register Read Timing 84 Figure 8 3 Address Table Write Timing...

Page 11: ...using a RocketIO transceiver 117 Figure 11 4 1 Gigabit Ethernet MAC Extended to Include 1000BASE X PCS and PMA using the RocketIO transceiver 118 Figure 11 5 Interfacing the Ethernet Statistics to the...

Page 12: ...12 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 R DISCONTINUED PRODUCT...

Page 13: ...with the Core Table 4 1 Degree of Difficulty for Various Implementations 38 Chapter 5 Using the Client Side Data Path Table 5 1 Abbreviations Used in Timing Diagrams 39 Table 5 2 Bit Definition for th...

Page 14: ...Core Table 9 1 Input GMII Timing 97 Table 9 2 Input RGMII Timing 102 Chapter 10 Clocking and Resetting Chapter 11 Interfacing to Other Cores Table 11 1 Management Interface Transaction Types 121 Chap...

Page 15: ...rs including how to initialize the core generate and consume core packets and how to operate the Management Interface Chapter 9 Constraining the Core describes the constraints associated with the core...

Page 16: ...manuals See the User Guide for details Emphasis in text If a wire is drawn so that it overlaps the pin of a symbol the two nets are not connected Dark Shading Items that are not supported or reserved...

Page 17: ...Hyperlink to a website URL Go to www xilinx com for the latest speed files Acronym Spelled Out CLB Configurable Logic Block DCM Digital Clock Manager DDR Double Data Rate FCS Frame Check Sequence FPGA...

Page 18: ...CB Printed Circuit Board PCS Physical Coding Sublayer PHY physical side interface PMA Physical Medium Attachment PMD Physical Medium Dependent RGMII Reduced Gigabit Media Independent Interface SGMII S...

Page 19: ...in the 1 Gigabit Ethernet MAC Getting Started Guide Recommended Design Experience Although the GEMAC core is a fully verified solution the challenge associated with implementing a complete design var...

Page 20: ...arted Guide Xilinx cannot guarantee timing functionality or support of this product for designs that do not follow these guidelines Feedback Xilinx welcomes comments and suggestions about the GEMAC co...

Page 21: ...s a block diagram of the GEMAC core with all the major functional blocks and interfaces Descriptions of the functional blocks and interfaces are provided in the sections that follow Figure 2 1 Block D...

Page 22: ...se 31 of the IEEE 802 3 2005 standard The MAC may be configured to send pause frames and to act upon their reception These two behaviors can be configured independently Address Filter The Address Filt...

Page 23: ...ional Management Interface gtx_clk gmii_rx_clk mdc mdio_in gmii_rxd 7 0 gmii_txd 7 0 gmii_tx_en gmii_tx_er tx_data 7 0 tx_ack tx_underrun pause_req pause_val 15 0 host_clk host_opcode 1 0 host_addr 9...

Page 24: ...0 input provides the method of setting the unicast address used by the Address Filter Figure 2 3 Component Pinout for MAC without Optional Management Interface and with Optional Address Filter gmii_rx...

Page 25: ...thod for configuration of the core Figure 2 4 Component Pinout for MAC without Optional Management Interface or Optional Address Filter gmii_rx_clk gmii_rxd 7 0 gmii_txd 7 0 gmii_tx_en gmii_tx_er rese...

Page 26: ...on page 47 The Transmitter Interface is designed to be connected to internal device logic only Attempting to add external ports to this interface will result in a breakdown of the handshaking protocol...

Page 27: ...rx_data_valid Output gmii_rx_clk Control signal for the rx_data port rx_good_frame Output gmii_rx_clk Asserted at end of frame reception to indicate that the frame should be processed by the MAC clie...

Page 28: ...e performed over MDIO interface Bit 1 is also used as a read write control signal for configuration register access host_addr 9 0 Input host_clk Address of register to be accessed host_wr_data 31 0 In...

Page 29: ...Signal Pinout Signal Direction Description configuration_vector 67 0 Input Used to replace the functionality of the MAC Configuration Registers when the Management Interface is not used Note All bits...

Page 30: ...ck programmable frequency derived from host_clk mdio_in1 1 mdio_in mdio_out and mdio_tri can be connected to a Tri state buffer to create a bi directional mdio signal suitable for connection to an ext...

Page 31: ...face GUI This chapter describes the GUI options used to generate and customize the core Graphical User Interface Figure 3 1 shows the main GEMAC core user GUI screen For general help starting and usin...

Page 32: ...and 4 to define the number of addresses that are present in the table This option is only available when the Management Interface and Address Filter have been selected The default is to use 4 address...

Page 33: ...the core using either Mentor Graphics ModelSim Cadence IUS or Synopsys VCS simulators See the 1 Gigabit Ethernet MAC Getting Started Guide for more information about the CORE Generator output files an...

Page 34: ...34 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 Chapter 3 Generating the Core R DISCONTINUED PRODUCT...

Page 35: ...ign Steps Generate the core from the Xilinx CORE Generator See Chapter 3 Generating the Core Using the Example Design as a Starting Point The GEMAC core is delivered through the CORE Generator with an...

Page 36: ...script in the implement directory to create a top level netlist for the design The script may also run the Xilinx tools map par and bitgen creating a bitstream that can be downloaded to a Xilinx devic...

Page 37: ...tatistics core in Chapter 11 Interfacing to Other Cores 10 Mbps 100 Mbps 1 Gbps Ethernet FIFO in Appendix A Using the Client Side FIFO You can synthesize the entire design using any synthesis tool The...

Page 38: ...timing constraints that should be applied See Chapter 9 Constraining the Core Use Supported Design Flows The core is pre synthesized and delivered as an NGC netlist The example implementation scripts...

Page 39: ...ce For port definition see Receiver Interface on page 27 Normal Frame Reception Figure 5 1 illustrates the timing of a normal inbound frame transfer The client must be prepared to accept data at any t...

Page 40: ...ield carrier extension if present the interframe gap following the frame and the preamble field of the next frame When Client Supplied FCS passing is enabled rx_data_valid is equal to zero between fra...

Page 41: ...ames are not enabled A value of 0x0000 to 0x002D is in the type length field In this situation the frame should be padded to minimum length If it is not padded to exactly minimum frame length the fram...

Page 42: ...ent it is also verified by the GEMAC core and rx_bad_frame asserted if the FCS check fails VLAN Tagged Frames Figure 5 4 illustrates the reception of a VLAN tagged frame if enabled The VLAN frame is p...

Page 43: ...ked against the actual data length received A value in the length type field that is less than decimal 46 is checked to see that the data field is padded to exactly 46 bytes so that the resultant fram...

Page 44: ...he optional Management Interface is present this is found in the unicast address configuration registers Table 8 8 and Table 8 9 page 82 If the Management Interface is not present the unicast address...

Page 45: ...frame is not padded to exactly 64 bytes This is independent of whether or not the length type field checks are enabled 24 Bad Opcode Asserted if the previous frame was error free and contained the sp...

Page 46: ...a multicast address in the destination address field 3 Broadcast Frame Asserted if the previous frame contained the broadcast address in the destination address field 2 FCS Error Asserted if the prev...

Page 47: ...the remainder of the data for the frame The end of frame is signalled to the GEMAC core by taking tx_data_valid low For maximum flexibility in switching and routing applications the Ethernet frame pa...

Page 48: ...of an aborted transfer An example of this situation is a FIFO connected to the client interface that empties before a frame transfer is complete When the client asserts tx_underrun during a frame tran...

Page 49: ...h When jumbo frame handling is enabled frames longer than the legal maximum are transmitted error free For more information on enabling and disabling Jumbo frame handling see Configuration Registers o...

Page 50: ...statistic_valid is asserted Figure 5 11 Byte valid is significant on every gtx_clk cycle Caution The statistic vectors in this release have been made compatible with the Tri Mode Ethernet MAC core The...

Page 51: ...Always at logic 0 19 VLAN Frame Asserted if the previous frame contained a VLAN identifier in the length type field when transmitter VLAN operation is enabled 18 5 Frame Length The length of the previ...

Page 52: ...istics conversion to previous core GEMAC core versions Version 8 5 tx_statistics_vector bit s Version 8 4 and earlier tx_statistics_vector bit s Notes 31 21 Bit 31 is equivalent to bit 21 of all previ...

Page 53: ...E 802 3 2005 standard The MAC may be configured to transmit pause requests and to act on their reception these modes of operation can be independently enabled or disabled See Flow Control Configuratio...

Page 54: ...e this data rate matching problem Flow Control Basics A MAC may transmit a pause control frame to request that its link partner cease transmission for a defined period of time For example the user MAC...

Page 55: ...e MAC Control opcode field Note MAC Control opcodes other than for pause flow control frames have recently been defined for Ethernet Passive Optical Networks The MAC control parameter field of the pau...

Page 56: ...the transmitter is inactive at the time of the pause request this pause control frame is transmitted immediately If the transmitter is currently busy the current frame being transmitted is allowed to...

Page 57: ...The length type field is matched against the MAC control type code The opcode field contents are matched against the Pause opcode If any of the previously described checks are false the frame is ignor...

Page 58: ...hreshold is implementation specific When the occupancy of the FIFO exceeds this occupancy initiate a single pause control frame from the user MAC with 0xFFFF used as the pause_quantum duration 0xFFFF...

Page 59: ...frame request 2 On receiving the pause control frame the link partner MAC ceases transmission 3 After the link partner MAC ceases transmission the occupancy of the FIFO in the user system rapidly emp...

Page 60: ...60 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 Chapter 6 Using Flow Control R DISCONTINUED PRODUCT...

Page 61: ...from the CORE Generator GUI see Chapter 3 Generating the Core For more information about the example design see the 1 Gigabit Ethernet MAC Getting Started Guide GMII Transmitter Logic Figure 7 1 illu...

Page 62: ...l GMII Transmitter Logic IPAD IBUFG IOB LOGIC gtx_clk BUFG gtx_clk_bufg gmii_tx_clk OBUF FDDRRSE IOB LOGIC OPAD D Q D Q 0 1 D Q gmii_txd 0 OBUF OPAD gmii_txd_reg 0 D Q gmii_tx_en OBUF OPAD gmii_tx_en_...

Page 63: ...optionally be used in other families Phase shifting may then be applied to the DCM to fine tune the setup and hold times at the GMII IOB input flip flops Fixed phase shift is applied to the DCM with t...

Page 64: ...the DCM Virtex 4 Devices For Virtex 4 families the generated reset from within the DCM reset module is further complicated Here the DCM reset pulse duration must be asserted for a minimum of 200 ms se...

Page 65: ...control inputs The IODELAY components are used in fixed delay mode where the attribute IDELAY_VALUE determines the tap delay value An IDELAYCTRL primitive must be instantiated for this mode of operat...

Page 66: ...the physical transmitter interface of the core to create an external RGMII in a Spartan 3 device The signal names and logic precisely match those delivered with the example design when the RGMII is s...

Page 67: ...tput DDR register so the clock signal produced incurs on exactly the same delay as the data and control signals The rgmii_tx_clk clock signal is phase shifted by 90 degrees in the DCM with respect to...

Page 68: ...RGMII v2 0 specification The use of the BUFGMUX shown with one input connected to the DCM CLK90 output is included so that a reliable 125MHz clock source is always provided on global routing when the...

Page 69: ...also shows that the output transmitter signals are registered in the IOBs in ODDR components These components convert the input signals into one double data rate signal The ODDR outputs are passed thr...

Page 70: ...lling edges of gmii_rx_clk_bufg The signals are then registered inside the FPGA fabric before a final register stage to synchronize signals to the rising edge clock To achieve the required setup and h...

Page 71: ...d 0 IBUF IPAD D Q 1 Gigabit Ethernet MAC Core gmii_rxd_reg 0 gmii_rx_dv_reg gmii_rx_er_reg gmii_rx_clk gmii_rxd 0 gmii_rx_dv gmii_rx_er BUFG IOB LOGIC DCM CLKIN CLK0 FB gmii_rx_clk_bufg D Q D Q rgmii_...

Page 72: ...to low transition on this signal indicating that the DCM has lost lock a reset will be issued A timeout counter is enabled when the DCM is in the loss of lock state If following the timeout period the...

Page 73: ...t any level of example design HDL hierarchy Figure 7 8 External RGMII Receiver Logic for Virtex 4 Devices 1 Gigabit Ethernet MAC Core gmii_rxd_int 0 gmii_rx_dv_int gmii_rx_er_int gmii_rx_clk gmii_rxd...

Page 74: ...the outputs of the control IDDR component The IODELAY components are used to phase shift the input RGMII clock data and control signals to meet the setup and hold margins The IODELAY components are us...

Page 75: ...etween frames The signal names and logic shown exactly match those delivered with the example design when the RGMII is selected Figure 7 10 RGMII Inband Status Decoding Logic 1 Gigabit Ethernet MAC Co...

Page 76: ...sical layer device such as the MDIO port of the Xilinx Ethernet 1000BASE X PCS PMA or SGMII core See Chapter 11 Interfacing to Other Cores for more information Connecting the MDIO to an External PHY T...

Page 77: ...e Management Interface Optional on page 28 This interface is used for Configuring of the GEMAC core via the configuration registers Access through the MDIO interface to the management registers locate...

Page 78: ...isters available in the core are listed in Table 8 2 As shown the address has some implicit don t care bits any access to an address in the ranges shown performs a 32 bit read or write from the same c...

Page 79: ...for example a MAC address of AA BB CC DD EE FF would be stored in Address 47 0 as 0xFFEEDDCCBBAA Table 8 4 Receiver Configuration Word 1 Bit Default Value Description 15 0 All 0s Pause frame MAC Sourc...

Page 80: ...frames up to the specified maximum 31 0 Reset When this bit is set to 1 the receiver will be reset The bit will then automatically revert to 0 This reset also sets all of the receiver configuration r...

Page 81: ...bit is 0 the MAC will only send frames up to the specified maximum 31 0 Reset When set to 1 the transmitter will be reset The bit will then automatically revert to 0 This reset will also set all of th...

Page 82: ...0 All 0s Clock Divide 4 0 This value enters a logical equation which enables the mdc frequency to be set as a divided down ratio of the host_clk frequency 5 0 MDIO Enable When this bit is 1 the MDIO...

Page 83: ...address is ordered so the first byte received is the lowest positioned byte in the register for example a MAC address of AA BB CC DD EE FF would be stored in Address 47 0 as 0xFFEEDDCCBBAA Table 8 11...

Page 84: ...ould be 1 as shown in Figure 8 2 In this case the contents of the register appear on host_rd_data the host_clk edge after the register address is asserted onto host_addr Figure 8 1 Configuration Regis...

Page 85: ...not write set to 0 This is shown in Figure 8 3 Although it is shown in the figure there is no requirement for the two writes to be on adjacent cycles As shown in Figure 8 4 you must write to the Addr...

Page 86: ...rial data line mdio An MDIO bus in a system consists of a single Station Management STA master management entity and a number of MDIO Managed Device MMD slave entities Figure 8 5 illustrates a typical...

Page 87: ...code PHYAD PHY address REGAD Register address TA Turnaround Write Transaction Figure 8 6 shows a write transaction across the MDIO as defined by OP 01 The addressed MMD PHYAD device takes the 16 bit w...

Page 88: ...the MDIO interface of the GEMAC core The MDIO interface supplies a clock to the connected PHY mdc This clock is derived from the host_clk signal using the value in the Clock Divide 4 0 configuration r...

Page 89: ...action by asserting host_miim_rdy A read or write transaction on the MDIO is initiated by a pulse on the host_req signal This pulse is ignored if the MDIO interface already has a transaction in progre...

Page 90: ...mii_rx_clk Pause frame MAC Source Address 47 0 This address is used by the GEMAC core to match against the destination address of any incoming flow control frames and as the source address for any out...

Page 91: ...ter Configuration Word bit 29 gtx_clk Transmitter In Band FCS Enable When this bit is 1 the MAC transmitter will expect the FCS field to be pass in by the client When it is 0 the MAC transmitter will...

Page 92: ...error checks as described in Length Type Field Error Checks on page 43 When this bit is set to 0 the length type field checks will be performed this is normal operation 64 Address Filter Mode bit 31...

Page 93: ...s a sufficient number of IOBs Operates at the following speed grades 4 for Spartan 3 Spartan 3E and Spartan 3A devices 10 for Virtex 4 FPGA 1 for Virtex 5 FPGA I O Location Constraints No specific I O...

Page 94: ...lowing UCF syntax shows the necessary constraints being applied to the clock signal which is routed to the gmii_rx_clk port of the core Set the Receiver clock period constraints please do not relax NE...

Page 95: ...sources the following constraints must always be applied Flow Control logic reclocking INST gmac_core BU2 U0 FLOW RX_PAUSE GOOD_FRAME_TO_TX TNM flow_rx_to_tx INST gmac_core BU2 U0 FLOW RX_PAUSE PAUSE_...

Page 96: ...ed into the following descriptions to provide examples These examples should be studied in conjunction with the HDL source code for the example design and with the description Implementing External GM...

Page 97: ..._rx_dv TNM IN_GMII TIMEGRP IN_GMII OFFSET IN 2 1 ns VALID 2 2 ns BEFORE gmii_rx_clk The constraints defined in the preceding lines have a built in 10 tolerance this allows all combinations of the exam...

Page 98: ...ee Understanding Timing Reports for GMII Setup Hold Timing The following constraint shows an example of setting the delay value for one of these IODELAY components Data Control bits can be adjusted in...

Page 99: ...lock s Phase gmii_rx_dv 1 531 R 0 141 R gmii_rx_clk_bufg 0 000 gmii_rx_er 1 531 R 0 141 R gmii_rx_clk_bufg 0 000 gmii_rxd 0 1 531 R 0 141 R gmii_rx_clk_bufg 0 000 gmii_rxd 1 1 525 R 0 135 R gmii_rx_cl...

Page 100: ...met it may not be immediately obvious how the results relate to Figure 9 1 The following is an example for the GMII report from a Virtex 5 device where the clock has been delayed to meet the setup ho...

Page 101: ...or the example design and with the description Implementing External GMII on page 61 RGMII IOB Constraints The following constraints target the flip flops that are inferred in the top level HDL file f...

Page 102: ...straints for this core RGMII Input Setup Hold Timing Figure 9 3 and Table 9 2 illustrate the setup and hold time window for the input RGMII signals This is the worst case data valid window presented t...

Page 103: ...ple RGMII pinout in the particular device The setup hold timing which is achieved after place and route is reported in the data sheet section of the TRCE report created by the implement script For cus...

Page 104: ...ign to link the instance of the IDELAYCTRL to the IODELAY components used on the RGMII These constraints aid the Xilinx tools in automatic IDELAYCTRL placement Group IODELAY and IDELAYCTRL components...

Page 105: ...al Clock s Phase rgmii_rx_ctl 3 352 R 4 300 R not_rgmii_rx_clk_bufg 4 938 0 661 R 0 284 R rgmii_rx_clk_bufg 0 938 rgmii_rxd 0 3 384 R 4 332 R not_rgmii_rx_clk_bufg 4 938 0 629 R 0 316 R rgmii_rx_clk_b...

Page 106: ...ample for the RGMII report from a Virtex 5 device where the clock has been delayed to meet the setup hold requirements Data Sheet report All values displayed in nanoseconds ns Setup Hold to clock rgmi...

Page 107: ...epresents 0 893 ns relative to the following rising edge of the clock since the IDELAY has acted to delay the clock by an entire period when measured from the input flip flop This is less than the 1 n...

Page 108: ...108 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 Chapter 9 Constraining the Core R DISCONTINUED PRODUCT...

Page 109: ...illustrates the clock management used with an external GMII interface All clocks illustrated have a frequency of 125 MHz The clock gtx_clk must be provided to the GEMAC core This is a high quality cl...

Page 110: ...i_rxc will be received through an IBUFG This clock is routed into a DCM where it is used to generate phase shifted clock signals for use in the RGMII receiver logic A fixed phase shift value is applie...

Page 111: ...transmitter clock domain across the device As a general rule a common receiver clock domain is not possible Each core receives an independent receiver clock from the PHY attached to the other end of...

Page 112: ...vides controllable skews on the reset nets within the design Figure 10 4 Clock Management Logic with External RGMII Multiple Cores IBUFG BUFG gtx_clk rgmii_rxc1 gmii_rx_clk gmii_rx_clk gtx_clk gtx_clk...

Page 113: ...ices use RocketIO GTX transceivers After the first introduction of a device specific RocketIO transceiver all subsequent references use the generic term RocketIO transceiver 1000BASE X parallel Ten Bi...

Page 114: ...Buffer in the Ethernet 1000BASE X PCS PMA or SGMII core the entire GMII is synchronous to a single clock domain For this reason gtx_clk is used as the 125 MHz reference clock for both cores and the t...

Page 115: ...bit Ethernet MAC Extended to Include 1000BASE X PCS and PMA using a RocketIO Transceiver 1 Gigabit Ethernet MAC LogiCORE gmii_rx_clk gmii_rxd 7 0 gmii_rx_dv gmii_rx_er gmii_txd 7 0 gmii_tx_en gmii_tx_...

Page 116: ...A or SGMII core to access its embedded configuration and status registers See Using the Optional Management Interface Due to the embedded Receiver Elastic Buffer in the Ethernet 1000BASE X PCS PMA or...

Page 117: ...be connected to that of the Ethernet 1000BASE X PCS PMA or SGMII core to access its embedded configuration and status registers See Using the Optional Management Interface Figure 11 3 1 Gigabit Ethern...

Page 118: ...d clock management logic required to interface the GEMAC core to the Ethernet 1000BASE X PCS PMA or SGMII core when used in 1000BASE X mode with PMA using the device specific RocketIO transceiver Figu...

Page 119: ...PMA using the device specific RocketIO transceiver The only difference is that the Ethernet 1000BASE X PCS PMA or SGMII core is generated with the SGMII option See Integration to Provide 1000BASE X P...

Page 120: ...ernet MAC host_clk host_addr 8 0 host_addr 9 host_req host_miim_sel host_wr_data 31 0 host_rd_data 31 0 I0 I1 S host_clk host_addr 8 0 host_addr 9 host_req host_miim_sel host_wr_data 31 0 host_rd_data...

Page 121: ...tics and logic 1 when writing and reading to the MAC configuration registers Using the host_miim_sel signal to differentiate between a statistical counter read and a MAC initiated MDIO transaction Thi...

Page 122: ...122 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 Chapter 11 Interfacing to Other Cores R DISCONTINUED PRODUCT...

Page 123: ...hesis and Verification Design Guide included in your Xilinx software installation The unit delay structural model of the GEMAC core can be found in the CORE Generator project directory Details of the...

Page 124: ...files in the project list An XST script file top_level_module_name scr containing your required synthesis options To synthesize the design run xst ifn top_level_module_name scr See the XST User Guide...

Page 125: ...d on constraints included in the optional PCF file An example of the trce command is trce o top_level_module_name twr top_level_module_name ncd top_level_module_name pcf Generating a Bitstream To crea...

Page 126: ...nformation about setting up your simulator to use the pre implemented model see the Xilinx Synthesis and Verification Design Guide included in your Xilinx software installation Other Implementation In...

Page 127: ...providing a buffer between the MAC and the user s logic The FIFO implements a LocalLink user interface see Overview of LocalLink Interface on page 130 allowing a direct connection to other LocalLink m...

Page 128: ...tx_data_valid Output tx_clk Valid signal for data tx_ack Input tx_clk Ack signal from MAC tx_underrun Output tx_clk Underrun signal to MAC tx_collision Input tx_clk Collision indication from MAC Tie...

Page 129: ...ta received from MAC rx_data_valid Input rx_clk Valid signal for data rx_good_frame Input rx_clk Indicates if frame is valid and should be accepted by client rx_bad_frame Input rx_clk Indicates if fra...

Page 130: ...om source to destination The individual packet boundaries are marked by the sof_n and eof_n signals For more information on the LocalLink interface see to Xilinx Application Note XAPP691 Parameterizab...

Page 131: ...rdless of whether it is a good or bad frame The signal rx_overflow is then asserted Situations in which the memory may overflow are The FIFO may overflow if the user is reading data from the FIFO at a...

Page 132: ...ped by the FIFO This ensures that the LocalLink interface does not lock up For this reason it is recommended that the FIFO not be used with the GEMAC in jumbo frame mode for frames larger than 4000 by...

Page 133: ...sted with the Ethernet 1000BASE X PCS PMA or SGMII core from Xilinx This follows the architecture shown in Figure 11 2 page 115 A test platform was built around these cores including a back end FIFO c...

Page 134: ...134 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 Appendix B Core Verification Compliance and Interoperability R DISCONTINUED PRODUCT...

Page 135: ...h precise delay and impedance matching for all the GMII RGMII receiver data bus and control signals You must determine the best DCM setting phase shift to ensure that the target system has the maximum...

Page 136: ...changes dramatically In eight phase shift settings or less the system can transition from no errors to exhibiting errors Checking the operational edge at a step size of two on more than one board ref...

Page 137: ...data octet appears on gmii_txd 7 0 of the physical side GMII style interface the latency through the core in the transmit direction is 9 clock periods of gtx_clk Receive Path Latency As measured from...

Page 138: ...138 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 Appendix D Core Latency R DISCONTINUED PRODUCT...

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