microDXP Technical Reference Manual
Version 3.15
October 7, 2019
51
and in the complexity of the electronics required to generate (usually from stored
coefficients) normalized {W
i
} sets on a pulse-by-pulse basis. One such commercial system
exists which can process over 1 Mcps, but it costs over $15K per channel.
The DXP processing system developed by XIA takes a different approach because it was
optimized for very high-speed operation and low cost per channel. It implements a fixed
length filter with all W
i
values equal to unity and in fact computes this sum afresh for each
new signal value k. Thus the equation implemented is as shown below, where the filter
length is L and the gap is G.
𝐿 𝑉
𝑥,𝑘
=
∑
𝑉
𝑖
𝑘
𝑖=𝑘−𝐿+1
−
∑
𝑉
𝑖
𝑘−𝐿−𝐺
𝑖=𝑘−2𝐿−𝐺+1
Equation 4-3
The factor L multiplying V
x,k
arises because the sum of the weights here is not normalized.
Accommodating this factor is trivial within the FPGA. The operations are carried out using
hardwired logic in a field programmable gate array (FPGA) that is called the FiPPI because
it implements Filtering, Peak capture, and Pileup Inspection.
In the FiPPI, Equation 4-3 is actually implemented by noting the recursion relationship
between V
x,k
and V
x,k-1
, which is:
L V
x,k
= L V
x,k-1
+ V
k
- V
k-L
- V
k-L-G
+ V
k-2L-G
Equation 4-4
While this relationship is very simple, it is still very effective. In the first place, this is the
digital equivalent of triangular (or trapezoidal if G=0) filtering which is the analog
industry’s standard for high rate processing. In the second place, one can show theoretically
that if the noise in the signal is white (i.e. Gaussian distributed) above and below the step,
which is typically the case for the short shaping times used for high signal rate processing,
then the average in Equation 4-4 actually gives the best estimate of V
x
in the least squares
sense. This, of course, is why triangular filtering has been preferred at high rates.
Triangular filtering with time variant filter lengths can, in principle, achieve both somewhat
superior resolution and higher throughputs but comes at the cost of a significantly more
complex circuit and a rate dependent resolution, which is unacceptable for many types of
precise analysis. In practice, XIA’s design has been found to duplicate the energy
resolution of the best analog shapers while approximately doubling their throughput,
providing experimental confirmation of the validity of the approach.
A practical limitation on the implementation of Equation 4-4 is that two FIFO memories
are required, one of length L and one of Length L+G. Since memory space is limited in
FPGAs, we have restricted our designs to values of L+G less than 1024. At the default
sample rate 40 MSPS, this corresponds to a peaking time of about 24
s.
4.3 Trapezoidal Filtering in the DXP
From this point onward, we will only consider trapezoidal filtering as it is implemented in
the DXP according to Equation 4-3 and Equation 4-4. The result of applying such a filter
with Length L = 20 and Gap G = 4 to the same data set of Figure 4-4 is shown in Figure
4-5. The filter output V
x
is clearly trapezoidal in shape and has a rise time equal to L, a
flat-top equal to G, and a symmetrical fall time equal to L. The base width, which is a first-
