WM8510-EV1M
w
Rev 1.1 April 2006
47
MCLK
GND
H1
Figure 34 Timing Connections From DSP Platform
The digital inputs to the WM8510 have a CMOS threshold (i.e. Logic High (min) = DBVDD * 0.7;
Logic Low (max) = DBVDD * 0.3). These are met directly by the level shift IC outputs.
Also in Master mode the jumpers on H5 should be removed, disconnecting the digital output section
of the WM8510 evaluation board. The ADCDAT, BCLK and LRCLK signals from the WM8510
should then be connected to the DSP from header H6 running on the side of the WM8510.
The ADCDAT, BCLK and LRCLK signals should be taken direct from the WM8510 digital output as
the output side of the level-shift IC (U3) from the WM8510 is pulled up to +5V which may overdrive
and cause damage to the DSP inputs. The digital output levels of the WM8510 are Logic High (min)
= DBVDD * 0.7; Logic Low (max) = DBVDD * 0.3 which should meet the input level requirements of
most DSPs running at +3V supplies.
If the DSP is running with +5V supplies (and +5V tolerant inputs) then the connections from the
WM8510 evaluation board to the DSP should be made from H5 on the output side of the level-shift
IC from the WM8510 as shown in Figure 35. This will ensure that the DSP input level specifications
are met.
Figure 35 Connections To The DSP Platform (+5V tolerant input levels)
Summary of Contents for WM8510-EV1M
Page 1: ...WM8510 EV1M Evaluation Board User Handbook Rev 1 1...
Page 8: ...WM8510 EV1M w Rev 1 1 April 2006 8 INTERFACES Figure 1 Interfaces...
Page 14: ...WM8510 EV1M w Rev 1 1 April 2006 14 WM8510 BLOCK DIAGRAM Figure 4 WM8510 Block Diagram...
Page 31: ...WM8510 EV1M w Rev 1 1 April 2006 31 Figure 25 Analogue Output...
Page 32: ...WM8510 EV1M w Rev 1 1 April 2006 32 Figure 26 WM8510...
Page 34: ...WM8510 EV1M w Rev 1 1 April 2006 34 PCB LAYOUT Figure 29 Silkscreen Top...
Page 35: ...WM8510 EV1M w Rev 1 1 April 2006 35 Figure 30 Top Layer...
Page 36: ...WM8510 EV1M w Rev 1 1 April 2006 36 Figure 31 Bottom Layer...
