PPM-C407/Configuration
v1.0
www.winsystems.com
Page 32
7.8.14 J504 Digital Input/Output
The PPM-C407 supports 24 lines of digital input/output (DIO) via the Lattice MachX02
FPGA interfaced to the processor with the Low Pin Count (LPC) interface. These lines
maintain the WinSystems standard DIO register definition and by using the TI
TXS0108E level converters, all signals are 5 V tolerant.
Layout and Pin Reference:
The I/O is terminated at a Molex 501571-5007, 2x25, 1 mm pitch (Pico-Clasp™) right
angle locking header connector (WS G650-2050-7HB).
Matching connector: The mate is the Molex 501189-5010 housing with Molex
501193-2000 crimp pins. WinSystems cables simplify connections to the board:
•
CBL-DIO24-000-14: Pico-Clasp to unterminated
•
CBL-DIO24-001-12: Pico-Clasp to Pico-Clasp
•
CBL-DIO24-002-12: Pico-Clasp to 2x25, 0.1" pitch housing
Pin
Name
Pin
Name
1
Port 2 Bit 7
2
GND
3
Port 2 Bit 6
4
GND
5
Port 2 Bit 5
6
GND
7
Port 2 Bit 4
8
GND
9
Port 2 Bit 3
10
GND
11
Port 2 Bit 2
12
GND
13
Port 2 Bit 1
14
GND
15
Port 2 Bit 0
16
GND
17
Port 1 Bit 7
18
GND
19
Port 1 Bit 6
20
GND
21
Port 1 Bit 5
22
GND
23
Port 1 Bit 4
24
GND
25
Port 1 Bit 3
26
GND
27
Port 1 Bit 2
28
GND
29
Port 1 Bit 1
30
GND
31
Port 1 Bit 0
32
GND
33
Port 0 Bit 7
34
GND
35
Port 0 Bit 6
36
GND
37
Port 0 Bit 5
38
GND
39
Port 0 Bit 4
40
GND
41
Port 0 Bit 3
42
GND
43
Port 0 Bit 2
44
GND
45
Port 0 Bit 1
46
GND
47
Port 0 Bit 0
48
GND
49
+5 V
50
GND
49
50
2
1
PRELIMINARY
