EPX-C414/Configuration
v1.0
www.winsystems.com
Page 39
7.10.21 PC104 PC/104 Bus
The PC/104 bus is electrically equivalent to the ISA bus and is generated from LPC by
FPGA. Standard PC/104 I/O cards can be populated on EPX-C414's connectors, located
at PC104. The interface does not support hot swap capability. The PC/104 bus
connector pin definitions are provided below for reference. Refer to the PC/104 Bus
Specification for specific signal and mechanical specifications.
This interface is PC/104 version 2.5 compliant.
Layout and Pin Reference
Pin
Name
Pin
Name
Pin
Name
Pin
Name
A1
IOCHK#
B1
GND
A2
SD7
B2
RESET
A3
SD6
B3
+5V
A4
SD5
B4
IRQ9
A5
SD4
B5
NC
A6
SD3
B6
DRQ2
A7
SD2
B7
-12V
A8
SD1
B8
SRDY
D0
GND
C0
GND
A9
SD0
B9
+12V
D1
MEMCS16# C1
SBHE#
A10
IOCHRDY B10
KEY
D2
IOCS16#
C2
LA23
A11
AEN
B11
SMEMW#
D3
IRQ10
C3
LA22
A12
SA19
B12
SMEMR#
D4
IRQ11
C4
LA21
A13
SA18#
B13
IOW#
D5
IRQ12
C5
LA20
A14
SA17
B14
IOR#
D6
IRQ15
C6
LA19
A15
SA16
B15
DACK3#
D7
IRQ14
C7
LA18
A16
SA15
B16
DRQ3
D8
DACK0
C8
LA17
A17
SA14
B17
DACK1#
D9
DRQ0
C9
MEMR#
A18
SA13
B18
DRQ1
D10
DACK5#
C10
MEMW#
A19
SA12
B19
REFRESH#
D11
DRQ5
C11
SD8
A20
SA11
B20
BCLK
D12
DACK6#
C12
SD9
A21
SA10
B21
IRQ7
D13
DRQ6
C13
SD10
A22
SA9
B22
IRQ6
D14
DACK7#
C14
SD11
A23
SA8
B23
IRQ5
D15
DRQ7
C15
SD12
A24
SA7
B24
IRQ4
D16
+5V
C16
SD13
A25
SA6
B25
IRQ3
D17
MASTER#
C17
SD14
A26
SA5
B26
DACK2#
D18
GND
C18
SD15
A27
SA4
B27
TC
D19
GND
C19
KEY
A28
SA3
B28
BALE
A29
SA2
B29
+5V
A30
SA1
B30
OSC
A31
SA0
B31
GND
A32
GND
B32
GND
# = Active low signal
Shaded cells indicate power pins.
D0
D19
C0
C19
A1
A32
B1
B32
