EPX-C414/Configuration
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The following sections provide details on each of the internal registers.
7.6.1 Port 0 through 5 I/O
Each I/O bit in each of the six ports can be individually programmed for input or output.
Writing a 0 to a bit position causes the corresponding output pin to go to a
high-impedance state (pulled high by external 10 k
Ω
resistors), allowing it to be used as
an input. When used in the input mode, a read reflects the inverted state of the I/O pin,
such that a high on the pin reads as a 0 in the register. Writing a 1 to a bit position
causes that output pin to sink current (up to 12 mA), effectively pulling it low.
7.6.2 INT_PENDING
This read-only register reflects the combined state of the INT_ID0 through INT_ID2
registers. When any of the lower three bits are set, it indicates that an interrupt is
pending on the I/O port corresponding to the bit position(s) that are set.
Reading this register allows an interrupt service routine to quickly determine if any
interrupts are pending, and which I/O port has a pending interrupt.
7.6.3 PAGE/LOCK
This register serves two purposes. The upper two bits (D6 and D7) select the register
page in use. Bits 0-5 allow the I/O ports to be locked. Write a 1 to the I/O port position to
prohibit further writes to the corresponding I/O port.
Table 12:
Register Definitions
I/O Address Offset
Page 0
Page 1
Page 2
Page 3
00h
Port 0 I/O
Port 0 I/O
Port 0 I/O
Port 0 I/O
01h
Port 1 I/O
Port 1 I/O
Port 1 I/O
Port 1 I/O
02h
Port 2 I/O
Port 2 I/O
Port 2 I/O
Port 2 I/O
03h
Port 3 I/O
Port 3 I/O
Port 3 I/O
Port 3 I/O
04h
Port 4 I/O
Port 4 I/O
Port 4 I/O
Port 4 I/O
05h
Port 5 I/O
Port 5 I/O
Port 5 I/O
Port 5 I/O
06h
Int_Pending
Int_Pending
Int_Pending
Int_Pending
07h
Page/Lock
Page/Lock
Page/Lock
Page/Lock
08h
Reserved
Pol_0
Enab_0
Int_ID0
09h
Reserved
Pol_1
Enab_1
Int_ID1
0Ah
Reserved
Pol_2
Enab_2
Int_ID2
