EPX-C414/Configuration
v1.0
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Page 17
7.6.4 POL0 through POL2
These registers are accessible when Page 1 is selected. They allow interrupt polarity
selection on a port-by-port and bit-by-bit basis. Writing a 1 to a bit position selects the
rising edge detection interrupts. Writing a 0 to a bit position selects falling edge
detection interrupts.
7.6.5 ENAB0 through ENAB2
These registers are accessible when Page 2 is selected. They allow for port-by-port and
bit-by-bit enabling of the edge detection interrupts. When set to a 1, the edge detection
interrupt is enabled for the corresponding port and bit. When cleared to 0, the bit’s edge
detection interrupt is disabled. Note that this register can be used to individually clear a
pending interrupt by disabling and re-enabling the pending interrupt.
7.6.6 INT_ID0 through INT_ID2
These registers are accessible when Page 3 is selected. They are used to identify
currently pending edge interrupts. A bit, when read as a 1, indicates that an edge of the
polarity programmed into the corresponding polarity register has been recognized. Note
that a write to this register (value ignored) clears ALL the pending interrupts in this
register.
7.7 1 MB SRAM Registers
The EPX-C414 board provides 1 MB of battery-backed user SRAM. The 1 MB SRAM is
normally used as a solid-state disk device by configuring appropriate driver for your
operating systems.
For example, the DOS driver USSD.SYS can be used to make the SRAM appear as a
drive in the system by adding the following to config.sys.
Device =
c:\ussd.sys /mod:u /pad:210 /dsz:1024
The base address for the SRAM is located at 0210h.
There are four I/O registers used for accessing the memory array. The register definition
and usage is defined below.
Table 13:
Page Bits
Page
D7
D6
D5-D0
Page 0
0
0
1/0
Page 1
0
1
1/0
Page 2
1
0
1/0
Page 3
1
1
1/0
