VXI VT1433B, User Manual, Page: 180 / 203

Block Ready: A one (1) indicates that there is a block of data available to be
read from the Send Data registers. A zero (0) indicates that less than a full block
is available.
Data Ready: A one (1) indicates that there is at least one word (32 bits) of data
available in the Send Data register. A zero (0) indicates that there is not valid
data in the Send Data register.
ST Done: A one (1) indicates that the internal DSP has competed and passed its
self test.
Loaded: A one (1) indicates that the internal DSP has successfully booted and
has loaded a valid model code.
Done: A zero (0) indicates that the on-card microprocessor has not finished
processing the last command and the Err* bit is not valid. This bit is set and
cleared by the DSP.
Err*: A zero (0) indicates that an error has occurred in communicating with the
DSP (for example: invalid parameters). This bit is set and cleared by the DSP.
Ready: The meaning of this depends on the state of the Passed bit. While
Passed is false, a one(1) indicates that the device is in the Config Reg Init state
and the Model Code bits of the Device Type register are not valid, while a zero
(0) indicates that the device is in either the self test or failed state. When Passed
is true, a one (1) indicates that the DSP has finished its initialization and is ready
for normal operation, while a zero (0) indicates that the device is in the passed
state.
Passed: A zero (0) indicates that the device is in either the Hard Reset, Soft
Reset, Config Reg Init, Failed or Init Failed state. A one (1) indicates that the
device is in the passed state.
HW OK: A one (1) indicates that all the on-card FPGAs have successfully be
initialized.
Q Resp Ready (Query Response Ready): A one (1) indicates that the Query
Response Register is loaded and ready to be read. It is set by the DSP and
cleared in hardware by a write to the Command Register.
Cmd Ready: A one (1) indicates that the command register and parameter
register are available for writing. It is set by the DSP microprocessor and cleared
in hardware by a write to the Command Register. This bit, when zero (0)
additionally indicates that the Done bit is not valid.
VT1433B User's Guide
Register Definitions
A-6